Have you ever heard about Coreboot?
Coreboot is an open-source firmware project for various motherboards, notebooks, SBCs and so on.
It has many:
- contributors: some of them works full time and some of them are just hobbyist
- forks/derives: libreboot, Heads
- supported ISAs: x86, AMD64, ARM or Power
- ODM use-cases: System76, Chromebooks, Purism
Sometimes I can found motherboards, which was supported in the previous releases, sometimes I found boards which is currently supported and sometimes I start to work on my own motherboards: Asus A88XM-E, ASRock FM2A88M-HD+.
Support for most the AMD K8 mobos were dropped at the 4.9 version, many of these boards were unmaintained for a while and this is certainly true for the ASRock 939A785GMH too.
In order to try out this board, I had to:
- checkout the 4.8.1 version
- build the crossgcc
- configure the targer and build the ROM
As we are talking about really old source code and particularly really old (cross)GCC version, there were many glitches during the build of the tool chain.
Build of such old versions were fine at the time, but release after release GCC become less tolarent and introduce many new rulesets over the time. This can easily ends up at fixing the build tools, if you use a newer rolling distro, like Arch Linux.
I faced the following problems, during the build:
- dead URL for libelf
- fix GCC7 build issue
- missing an include for binutils
- add fix to GCCs linker
- GDB were not compatible with Guile 2.2: guile: Add support for Guile 2.2.
and so on. If you need to compile older CB releases, I recommend you to use the following Dockerfile:
loop0br/coreboot-compile
At the end, I built 3 different releases (4.6, 4.7 and 4.8.1), but unfortunately none of them booted up the board.
At the #coreboot room, I was told that some Bulldozer related changes broke many K8h and K10h boards:
- Patch set updated for coreboot: cpu/amd/family_10h-family_15h: Fix Family 15h multiple package support
- [coreboot] AMD codebase change, multiple mainboards affected
The status report from 2017 was also wrong, some way the configs were mixed up, as this board was for a
CONFIG_BOARD_ASROCK_G41C_GS=y.
You can see the console outputs below:
4.6
coreboot-4.6-2-g2c84d27a32-dirty Sun Jan 9 09:33:22 UTC 2022 romstage starting...
bsp_apicid=0x0
Enabling routing table for node 0 done.
Enabling SMP settings
01 nodes initialized.
Enabling UP settings
Disabling read/write/fill probes for UP... done.
coherent_ht_finalize
done
core0 started:
SBLink=00
NC node|link=00
rs780_early_setup()
k8_optimization()
rs780_por_init
sb700_early_setup()
sb700_devices_por_init()
sb700_devices_por_init(): SMBus Device, BDF:0-20-0
SMBus controller enabled, sb revision is A14
sb700_devices_por_init(): IDE Device, BDF:0-20-1
sb700_devices_por_init(): LPC Device, BDF:0-20-3
sb700_devices_por_init(): P2P Bridge, BDF:0-20-4
sb700_devices_por_init(): SATA Device, BDF:0-17-0
sb700_pmio_por_init()
begin msr fid, vid: hi=0x12040606, lo=0x40a0a0a
Current fid_cur: 0xa, fid_max: 0xa
Requested fid_new: 0xa
end msr fid, vid: hi=0x12040604, lo=0x40a0a0a
entering optimize_link_incoherent_ht
sysinfo->link_pair_num=0x1
entering ht_optimize_link
pos=0x8a, unfiltered freq_cap=0x8075
pos=0x8a, filtered freq_cap=0x75
pos=0xd2, unfiltered freq_cap=0x1e75
pos=0xd2, filtered freq_cap=0x1e75
freq_cap1=0x75, freq_cap2=0x1e75
dev1 old_freq=0x0, freq=0x6, needs_reset=0x1
dev2 old_freq=0x0, freq=0x6, needs_reset=0x1
width_cap1=0x11, width_cap2=0x11
dev1 input ln_width1=0x4, ln_width2=0x4
dev1 input width=0x1
dev1 output ln_width1=0x4, ln_width2=0x4
dev1 input|output width=0x11
old dev1 input|output width=0x11
dev2 input|output width=0x11
old dev2 input|output width=0x11
after ht_optimize_link for link pair 0, reset_needed=0x1
after optimize_link_read_pointers_chain, reset_needed=0x1
rs780_htinit cpu_ht_freq=6.
rs780_htinit: HT1 mode
needs_reset=0x1
ht reset -
coreboot-4.6-2-g2c84d27a32-dirty Sun Jan 9 09:33:22 UTC 2022 romstage starting...
bsp_apicid=0x0
Enabling routing table for node 0 done.
Enabling SMP settings
01 nodes initialized.
Enabling UP settings
Disabling read/write/fill probes for UP... done.
coherent_ht_finalize
done
core0 started:
SBLink=00
NC node|link=00
rs780_early_setup()
k8_optimization()
rs780_por_init
sb700_early_setup()
sb700_devices_por_init()
sb700_devices_por_init(): SMBus Device, BDF:0-20-0
SMBus controller enabled, sb revision is A14
sb700_devices_por_init(): IDE Device, BDF:0-20-1
sb700_devices_por_init(): LPC Device, BDF:0-20-3
sb700_devices_por_init(): P2P Bridge, BDF:0-20-4
sb700_devices_por_init(): SATA Device, BDF:0-17-0
sb700_pmio_por_init()
begin msr fid, vid: hi=0x12040604, lo=0x40a0a0a
end msr fid, vid: hi=0x12040604, lo=0x40a0a0a
entering optimize_link_incoherent_ht
sysinfo->link_pair_num=0x1
entering ht_optimize_link
pos=0x8a, unfiltered freq_cap=0x8075
pos=0x8a, filtered freq_cap=0x75
pos=0xd2, unfiltered freq_cap=0x1e75
pos=0xd2, filtered freq_cap=0x1e75
freq_cap1=0x75, freq_cap2=0x1e75
dev1 old_freq=0x6, freq=0x6, needs_reset=0x0
dev2 old_freq=0x6, freq=0x6, needs_reset=0x0
width_cap1=0x11, width_cap2=0x11
dev1 input ln_width1=0x4, ln_width2=0x4
dev1 input width=0x1
dev1 output ln_width1=0x4, ln_width2=0x4
dev1 input|output width=0x11
old dev1 input|output width=0x11
dev2 input|output width=0x11
old dev2 input|output width=0x11
after ht_optimize_link for link pair 0, reset_needed=0x0
after optimize_link_read_pointers_chain, reset_needed=0x0
rs780_htinit cpu_ht_freq=6.
rs780_htinit: HT1 mode
needs_reset=0x0
sysinfo->nodes: 1 sysinfo->ctrl: 000c8128 spd_addr: fff0b0bc
Ram1.00
setting up CPU00 northbridge registers
done.
Ram2.00
Unbuffered
Setting DualDIMMen
200MHz
RAM end at 0x00080000 kB
Lower RAM end at 0x00080000 kB
Ram3
Initializing memory: done
Handling memory hole at 0x00300000 (default)
Ram4
BSP overran lower stack boundary. Undefined behaviour may result!
Romstage handoff structure not added!
CBFS: 'Master Header Locator' located CBFS at [100:fffc0)
CBFS: Locating 'fallback/ramstage'
CBFS: Found @ offset d140 size 1009c
coreboot-4.6-2-g2c84d27a32-dirty Sun Jan 9 09:33:22 UTC 2022 ramstage starting...
Enumerating buses...
Show all devs... Before device enumeration.
Root Device: enabled 1
CPU_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
DOMAIN: 0000: enabled 1
PCI: 00:18.0: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:02.0: enabled 1
PCI: 00:03.0: enabled 0
PCI: 00:04.0: enabled 0
PCI: 00:05.0: enabled 0
PCI: 00:06.0: enabled 0
PCI: 00:07.0: enabled 0
PCI: 00:08.0: enabled 0
PCI: 00:09.0: enabled 1
PCI: 00:0a.0: enabled 1
PCI: 00:11.0: enabled 1
PCI: 00:12.0: enabled 1
PCI: 00:12.1: enabled 1
PCI: 00:12.2: enabled 1
PCI: 00:13.0: enabled 1
PCI: 00:13.1: enabled 1
PCI: 00:13.2: enabled 1
PCI: 00:14.0: enabled 1
I2C: 00:50: enabled 1
I2C: 00:51: enabled 1
I2C: 00:52: enabled 1
I2C: 00:53: enabled 1
PCI: 00:14.1: enabled 1
PCI: 00:14.2: enabled 1
PCI: 00:14.3: enabled 1
PNP: 002e.0: enabled 0
PNP: 002e.1: enabled 0
PNP: 002e.2: enabled 1
PNP: 002e.3: enabled 1
PNP: 002e.5: enabled 1
PNP: 002e.307: enabled 0
PNP: 002e.8: enabled 1
PNP: 002e.9: enabled 1
PNP: 002e.109: enabled 1
PNP: 002e.209: enabled 1
PNP: 002e.309: enabled 0
PNP: 002e.a: enabled 0
PNP: 002e.b: enabled 1
PNP: 002e.c: enabled 0
PCI: 00:14.4: enabled 1
PCI: 00:14.5: enabled 1
PCI: 00:18.1: enabled 1
PCI: 00:18.2: enabled 1
PCI: 00:18.3: enabled 1
Compare with tree...
Root Device: enabled 1
CPU_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
DOMAIN: 0000: enabled 1
PCI: 00:18.0: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:02.0: enabled 1
PCI: 00:03.0: enabled 0
PCI: 00:04.0: enabled 0
PCI: 00:05.0: enabled 0
PCI: 00:06.0: enabled 0
PCI: 00:07.0: enabled 0
PCI: 00:08.0: enabled 0
PCI: 00:09.0: enabled 1
PCI: 00:0a.0: enabled 1
PCI: 00:11.0: enabled 1
PCI: 00:12.0: enabled 1
PCI: 00:12.1: enabled 1
PCI: 00:12.2: enabled 1
PCI: 00:13.0: enabled 1
PCI: 00:13.1: enabled 1
PCI: 00:13.2: enabled 1
PCI: 00:14.0: enabled 1
I2C: 00:50: enabled 1
I2C: 00:51: enabled 1
I2C: 00:52: enabled 1
I2C: 00:53: enabled 1
PCI: 00:14.1: enabled 1
PCI: 00:14.2: enabled 1
PCI: 00:14.3: enabled 1
PNP: 002e.0: enabled 0
PNP: 002e.1: enabled 0
PNP: 002e.2: enabled 1
PNP: 002e.3: enabled 1
PNP: 002e.5: enabled 1
PNP: 002e.307: enabled 0
PNP: 002e.8: enabled 1
PNP: 002e.9: enabled 1
PNP: 002e.109: enabled 1
PNP: 002e.209: enabled 1
PNP: 002e.309: enabled 0
PNP: 002e.a: enabled 0
PNP: 002e.b: enabled 1
PNP: 002e.c: enabled 0
PCI: 00:14.4: enabled 1
PCI: 00:14.5: enabled 1
PCI: 00:18.1: enabled 1
PCI: 00:18.2: enabled 1
PCI: 00:18.3: enabled 1
Mainboard 939A785GMH/128M Enable. dev=0x0011faa0
Root Device scanning...
root_dev_scan_bus for Root Device
setup_bsp_ramtop, TOP MEM: msr.lo = 0x20000000, msr.hi = 0x00000000
setup_bsp_ramtop, TOP MEM2: msr.lo = 0x00000000, msr.hi = 0x00000000
setup_uma_memory: uma size 0x08000000, memory start 0x18000000
CPU_CLUSTER: 0 enabled
DOMAIN: 0000 enabled
CPU_CLUSTER: 0 scanning...
PCI: 00:18.3 siblings=0
Found Rev E or Rev F later single core
CPU: APIC: 00 enabled
scan_bus: scanning of bus CPU_CLUSTER: 0 took 0 usecs
DOMAIN: 0000 scanning...
PCI: pci_scan_bus for bus 00
PCI: 00:18.0 [1022/1100] bus ops
PCI: 00:18.0 [1022/1100] enabled
PCI: 00:18.1 [1022/1101] enabled
PCI: 00:18.2 [1022/1102] enabled
PCI: 00:18.3 [1022/1103] ops
PCI: 00:18.3 [1022/1103] enabled
PCI: 00:18.0 scanning...
do_hypertransport_scan_chain for bus 00
rs780_enable: dev=001217c0, VID_DID=0x96011022
Bus-0, Dev-0, Fun-0.
enable_pcie_bar3()
gpp_sb_init nb_dev=0x0, dev=0x40, port=0x8
NB_PCI_REG04 = 6.
NB_PCI_REG84 = 3000095.
NB_PCI_REG4C = 52042.
PCI: 00:00.0 [1022/9601] enabled
Capability: type 0x08 @ 0xc4
flags: 0x0180
PCI: 00:00.0 count: 000c static_count: 0015
PCI: 00:00.0 [1022/9601] enabled next_unitid: 0015
PCI: pci_scan_bus for bus 00
rs780_enable: dev=001217c0, VID_DID=0x96011022
Bus-0, Dev-0, Fun-0.
enable_pcie_bar3()
gpp_sb_init nb_dev=0x0, dev=0x40, port=0x8
NB_PCI_REG04 = 6.
NB_PCI_REG84 = 3000095.
NB_PCI_REG4C = 52042.
PCI: 00:00.0 [1022/9601] enabled
rs780_enable: dev=00121720, VID_DID=0x96021022
Bus-0, Dev-1, Fun-0.
GC is accessible from now on.
Capability: type 0x08 @ 0x44
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0x44
Capability: type 0x08 @ 0x44
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0x44
Capability: type 0x0d @ 0xb0
PCI: 00:01.0 [1022/9602] enabled
rs780_enable: dev=00121680, VID_DID=0x96031022
Bus-0, Dev-2,3, Fun-0. enable=1
rs780_gfx_init, nb_dev=0x001217c0, dev=0x00121680, port=0x2.
misc 28 = 1
rs780_gfx_init step5.9.12.1.
rs780_gfx_init step5.9.12.3.
rs780_gfx_init step5.9.12.9.
rs780_gfx_init step1.
device = 2
rs780_gfx_init single_port_configuration.
PcieLinkTraining port=2:lc current state=2030400
rs780_gfx_init single_port_configuration step12.
rs780_gfx_init single_port_configuration step13.
rs780_gfx_init single_port_configuration step14.
PCI: Static device PCI: 00:02.0 not found, disabling it.
rs780_enable: dev=001215e0, VID_DID=0xffffffff
Bus-0, Dev-2,3, Fun-0. enable=0
rs780_enable: dev=00121540, VID_DID=0xffffffff
Bus-0, Dev-4,5,6,7, Fun-0. enable=0
rs780_enable: dev=001214a0, VID_DID=0xffffffff
Bus-0, Dev-4,5,6,7, Fun-0. enable=0
rs780_enable: dev=00121400, VID_DID=0xffffffff
Bus-0, Dev-4,5,6,7, Fun-0. enable=0
rs780_enable: dev=00121360, VID_DID=0xffffffff
Bus-0, Dev-4,5,6,7, Fun-0. enable=0
rs780_enable: dev=001212c0, VID_DID=0x960a1022
Bus-0, Dev-8, Fun-0. enable=0
rs780_enable: dev=00121220, VID_DID=0x96081022
Bus-0, Dev-9, 10, Fun-0. enable=1
gpp_sb_init nb_dev=0x0, dev=0x48, port=0x9
PcieLinkTraining port=9:lc current state=10203
PcieTrainPort port=0x9 result=0
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
PCI: 00:09.0 subordinate bus PCI Express
PCI: 00:09.0 [1022/9608] enabled
rs780_enable: dev=00121180, VID_DID=0x96091022
Bus-0, Dev-9, 10, Fun-0. enable=1
gpp_sb_init nb_dev=0x0, dev=0x50, port=0xa
PcieLinkTraining port=a:lc current state=a0b0f10
addr=e0000000,bus=0,devfn=50
PcieTrainPort reg=0x10000
PcieTrainPort port=0xa result=1
disable_pcie_bar3()
rs780 unused GPP ports bitmap=0x2fc, force disabled
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
PCI: 00:0a.0 subordinate bus PCI Express
PCI: 00:0a.0 [1022/9609] enabled
sb7xx_51xx_enable()
PCI: 00:11.0 [1002/4390] ops
PCI: 00:11.0 [1002/4390] enabled
sb7xx_51xx_enable()
PCI: 00:12.0 [1002/4397] ops
PCI: 00:12.0 [1002/4397] enabled
sb7xx_51xx_enable()
PCI: 00:12.1 [1002/4398] ops
PCI: 00:12.1 [1002/4398] enabled
sb7xx_51xx_enable()
PCI: 00:12.2 [1002/4396] ops
PCI: 00:12.2 [1002/4396] enabled
sb7xx_51xx_enable()
PCI: 00:13.0 [1002/4397] ops
PCI: 00:13.0 [1002/4397] enabled
sb7xx_51xx_enable()
PCI: 00:13.1 [1002/4398] ops
PCI: 00:13.1 [1002/4398] enabled
sb7xx_51xx_enable()
PCI: 00:13.2 [1002/4396] ops
PCI: 00:13.2 [1002/4396] enabled
sb7xx_51xx_enable()
PCI: 00:14.0 [1002/4385] bus ops
PCI: 00:14.0 [1002/4385] enabled
sb7xx_51xx_enable()
PCI: 00:14.1 [1002/439c] ops
PCI: 00:14.1 [1002/439c] enabled
sb7xx_51xx_enable()
PCI: 00:14.2 [1002/4383] ops
PCI: 00:14.2 [1002/4383] enabled
sb7xx_51xx_enable()
PCI: 00:14.3 [1002/439d] bus ops
PCI: 00:14.3 [1002/439d] enabled
sb7xx_51xx_enable()
PCI: 00:14.4 [1002/4384] bus ops
PCI: 00:14.4 [1002/4384] enabled
sb7xx_51xx_enable()
PCI: 00:14.5 [1002/4399] ops
PCI: 00:14.5 [1002/4399] enabled
PCI: 00:01.0 scanning...
do_pci_scan_bridge for PCI: 00:01.0
PCI: pci_scan_bus for bus 01
PCI: 01:05.0 [1002/0000] ops
rs780_internal_gfx_enable dev = 0x00179278, nb_dev = 0x001217c0.
Sysmem TOM = 0_20000000
Sysmem TOM2 = 0_0
PCI: 01:05.0 [1002/9710] enabled
scan_bus: scanning of bus PCI: 00:01.0 took 0 usecs
PCI: 00:09.0 scanning...
do_pci_scan_bridge for PCI: 00:09.0
PCI: pci_scan_bus for bus 02
scan_bus: scanning of bus PCI: 00:09.0 took 0 usecs
PCI: 00:0a.0 scanning...
do_pci_scan_bridge for PCI: 00:0a.0
PCI: pci_scan_bus for bus 03
PCI: 03:00.0 [10ec/8168] enabled
Capability: type 0x01 @ 0x40
Capability: type 0x05 @ 0x50
Capability: type 0x10 @ 0x70
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
scan_bus: scanning of bus PCI: 00:0a.0 took 0 usecs
PCI: 00:14.0 scanning...
scan_generic_bus for PCI: 00:14.0
bus: PCI: 00:14.0[0]->I2C: 01:50 enabled
bus: PCI: 00:14.0[0]->I2C: 01:51 enabled
bus: PCI: 00:14.0[0]->I2C: 01:52 enabled
bus: PCI: 00:14.0[0]->I2C: 01:53 enabled
scan_generic_bus for PCI: 00:14.0 done
scan_bus: scanning of bus PCI: 00:14.0 took 0 usecs
PCI: 00:14.3 scanning...
scan_lpc_bus for PCI: 00:14.3
PNP: 002e.0 disabled
PNP: 002e.1 disabled
PNP: 002e.2 enabled
PNP: 002e.3 enabled
PNP: 002e.5 enabled
PNP: 002e.307 disabled
PNP: 002e.8 enabled
PNP: 002e.9 enabled
PNP: 002e.109 enabled
PNP: 002e.209 enabled
PNP: 002e.309 disabled
PNP: 002e.a disabled
PNP: 002e.b enabled
PNP: 002e.c disabled
PNP: 002e.6 enabled
scan_lpc_bus for PCI: 00:14.3 done
scan_bus: scanning of bus PCI: 00:14.3 took 0 usecs
PCI: 00:14.4 scanning...
do_pci_scan_bridge for PCI: 00:14.4
PCI: pci_scan_bus for bus 04
PCI: 04:05.0 [10ec/8139] enabled
scan_bus: scanning of bus PCI: 00:14.4 took 0 usecs
scan_bus: scanning of bus PCI: 00:18.0 took 0 usecs
DOMAIN: 0000 passpw: enabled
scan_bus: scanning of bus DOMAIN: 0000 took 0 usecs
root_dev_scan_bus for Root Device done
scan_bus: scanning of bus Root Device took 0 usecs
done
found VGA at PCI: 01:05.0
Setting up VGA for PCI: 01:05.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:01.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:18.0
Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
Allocating resources...
Reading resources...
Root Device read_resources bus 0 link: 0
CPU_CLUSTER: 0 read_resources bus 0 link: 0
CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
DOMAIN: 0000 read_resources bus 0 link: 0
VGA: PCI: 00:18.0 (aka node 0) link 0 has VGA device
PCI: 00:18.0 read_resources bus 0 link: 0
PCI: 00:00.0 register 1c(00000004), read-only ignoring it
PCI: 00:01.0 read_resources bus 1 link: 0
rs780_gfx_read_resources.
PCI: 00:01.0 read_resources bus 1 link: 0 done
PCI: 00:09.0 register 10(ffffffff), read-only ignoring it
PCI: 00:09.0 register 14(ffffffff), read-only ignoring it
PCI: 00:09.0 register 38(ffffffff), read-only ignoring it
PCI: 00:09.0 read_resources bus 2 link: 0
PCI: 00:09.0 read_resources bus 2 link: 0 done
PCI: 00:0a.0 read_resources bus 3 link: 0
PCI: 00:0a.0 read_resources bus 3 link: 0 done
PCI: 00:14.0 read_resources bus 1 link: 0
I2C: 01:50 missing read_resources
I2C: 01:51 missing read_resources
I2C: 01:52 missing read_resources
I2C: 01:53 missing read_resources
PCI: 00:14.0 read_resources bus 1 link: 0 done
PCI: 00:14.3 read_resources bus 0 link: 0
PCI: 00:14.3 read_resources bus 0 link: 0 done
PCI: 00:14.4 read_resources bus 4 link: 0
PCI: 00:14.4 read_resources bus 4 link: 0 done
PCI: 00:18.0 read_resources bus 0 link: 0 done
PCI: 00:18.0 read_resources bus 0 link: 1
PCI: 00:18.0 read_resources bus 0 link: 1 done
PCI: 00:18.0 read_resources bus 0 link: 2
PCI: 00:18.0 read_resources bus 0 link: 2 done
DOMAIN: 0000 read_resources bus 0 link: 0 done
Root Device read_resources bus 0 link: 0 done
Done reading resources.
Show resources in subtree (Root Device)...After reading.
Root Device child on link 0 CPU_CLUSTER: 0
CPU_CLUSTER: 0 child on link 0 APIC: 00
APIC: 00
DOMAIN: 0000 child on link 0 PCI: 00:18.0
DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
PCI: 00:18.0 child on link 0 PCI: 00:00.0
PCI: 00:18.0 resource base 3 size 0 align 0 gran 0 limit 1fff000 flags 1 index 1c0
PCI: 00:18.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80100 index 0
PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 81200 index 2
PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80200 index 1
PCI: 00:18.0 resource base a0000 size 20000 align 0 gran 0 limit ffffffff flags c0000200 index 4
PCI: 00:00.0
PCI: 00:01.0 child on link 0 PCI: 01:05.0
PCI: 00:01.0 resource base 0 size 0 align 12 gran 12 limit 1ffffff flags 80102 index 1c
PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 81202 index 24
PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
PCI: 01:05.0
PCI: 01:05.0 resource base 0 size 8000000 align 27 gran 27 limit ffffffff flags 1200 index 10
PCI: 01:05.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 14
PCI: 01:05.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 200 index 18
PCI: 01:05.0 resource base 0 size 100000 align 20 gran 20 limit ffffffff flags 200 index 24
PCI: 00:02.0
PCI: 00:03.0
PCI: 00:04.0
PCI: 00:05.0
PCI: 00:06.0
PCI: 00:07.0
PCI: 00:08.0
PCI: 00:09.0
PCI: 00:0a.0 child on link 0 PCI: 03:00.0
PCI: 00:0a.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
PCI: 00:0a.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
PCI: 00:0a.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
PCI: 03:00.0
PCI: 03:00.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10
PCI: 03:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 1201 index 18
PCI: 03:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 1201 index 20
PCI: 03:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 2200 index 30
PCI: 00:11.0
PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
PCI: 00:11.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20
PCI: 00:11.0 resource base 0 size 400 align 12 gran 10 limit ffffffff flags 200 index 24
PCI: 00:12.0
PCI: 00:12.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
PCI: 00:12.1
PCI: 00:12.1 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
PCI: 00:12.2
PCI: 00:12.2 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 10
PCI: 00:13.0
PCI: 00:13.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
PCI: 00:13.1
PCI: 00:13.1 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
PCI: 00:13.2
PCI: 00:13.2 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 10
PCI: 00:14.0 child on link 0 I2C: 01:50
PCI: 00:14.0 resource base fec00000 size 1000 align 8 gran 8 limit ffffffff flags d0000200 index 74
PCI: 00:14.0 resource base feb00000 size 1000 align 8 gran 8 limit ffffffff flags d0000200 index 9c
PCI: 00:14.0 resource base fed00000 size 400 align 8 gran 8 limit ffffffff flags d0000200 index b4
PCI: 00:14.0 resource base b00 size 10 align 8 gran 8 limit ffff flags d0000100 index 90
PCI: 00:14.0 resource base b20 size 10 align 8 gran 8 limit ffff flags d0000100 index 58
I2C: 01:50
I2C: 01:51
I2C: 01:52
I2C: 01:53
PCI: 00:14.1
PCI: 00:14.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
PCI: 00:14.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
PCI: 00:14.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
PCI: 00:14.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
PCI: 00:14.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20
PCI: 00:14.2
PCI: 00:14.2 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
PCI: 00:14.3 child on link 0 PNP: 002e.0
PCI: 00:14.3 resource base 0 size 1 align 12 gran 0 limit ffffffff flags 200 index a0
PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
PNP: 002e.0
PNP: 002e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
PNP: 002e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
PNP: 002e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags c0000800 index 74
PNP: 002e.1
PNP: 002e.1 resource base 378 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
PNP: 002e.1 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
PNP: 002e.2
PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
PNP: 002e.3
PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
PNP: 002e.5
PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 60
PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 62
PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
PNP: 002e.5 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 72
PNP: 002e.307
PNP: 002e.8
PNP: 002e.9
PNP: 002e.109
PNP: 002e.209
PNP: 002e.309
PNP: 002e.a
PNP: 002e.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
PNP: 002e.b
PNP: 002e.b resource base 290 size 2 align 1 gran 1 limit 7ff flags c0000100 index 60
PNP: 002e.b resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
PNP: 002e.c
PNP: 002e.6
PNP: 002e.6 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 62
PCI: 00:14.4 child on link 0 PCI: 04:05.0
PCI: 00:14.4 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 81202 index 24
PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
PCI: 04:05.0
PCI: 04:05.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10
PCI: 04:05.0 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 14
PCI: 00:14.5
PCI: 00:14.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
PCI: 00:18.1
PCI: 00:18.2
PCI: 00:18.3
PCI: 00:18.3 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 200 index 94
DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
PCI: 00:18.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 00:01.0 io: base: 0 size: 0 align: 12 gran: 12 limit: 1ffffff
PCI: 01:05.0 14 * [0x0 - 0xff] io
PCI: 00:01.0 io: base: 100 size: 1000 align: 12 gran: 12 limit: ffff done
PCI: 00:0a.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
PCI: 03:00.0 10 * [0x0 - 0xff] io
PCI: 00:0a.0 io: base: 100 size: 1000 align: 12 gran: 12 limit: ffff done
PCI: 00:14.4 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 04:05.0 10 * [0x0 - 0xff] io
PCI: 00:14.4 io: base: 100 size: 1000 align: 12 gran: 12 limit: ffff done
PCI: 00:01.0 1c * [0x0 - 0xfff] io
PCI: 00:0a.0 1c * [0x1000 - 0x1fff] io
PCI: 00:14.4 1c * [0x2000 - 0x2fff] io
PCI: 00:11.0 20 * [0x3000 - 0x300f] io
PCI: 00:14.1 20 * [0x3010 - 0x301f] io
PCI: 00:11.0 10 * [0x3020 - 0x3027] io
PCI: 00:11.0 18 * [0x3028 - 0x302f] io
PCI: 00:14.1 10 * [0x3030 - 0x3037] io
PCI: 00:14.1 18 * [0x3038 - 0x303f] io
PNP: 002e.6 62 * [0x3040 - 0x3047] io
PCI: 00:11.0 14 * [0x3048 - 0x304b] io
PCI: 00:11.0 1c * [0x304c - 0x304f] io
PCI: 00:14.1 14 * [0x3050 - 0x3053] io
PCI: 00:14.1 1c * [0x3054 - 0x3057] io
PCI: 00:18.0 io: base: 3058 size: 4000 align: 12 gran: 12 limit: 7ff done
PCI: 00:18.0 00 * [0x0 - 0x3fff] io
DOMAIN: 0000 io: base: 4000 size: 4000 align: 12 gran: 0 limit: 7ff done
DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
PCI: 00:18.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff
PCI: 00:01.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff
PCI: 01:05.0 10 * [0x0 - 0x7ffffff] prefmem
PCI: 00:01.0 prefmem: base: 8000000 size: 8000000 align: 27 gran: 20 limit: ffffffff done
PCI: 00:0a.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 03:00.0 20 * [0x0 - 0x3fff] prefmem
PCI: 03:00.0 18 * [0x4000 - 0x4fff] prefmem
PCI: 00:0a.0 prefmem: base: 5000 size: 100000 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:14.4 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 00:14.4 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
PCI: 00:01.0 24 * [0x0 - 0x7ffffff] prefmem
PCI: 00:0a.0 24 * [0x8000000 - 0x80fffff] prefmem
PCI: 00:18.0 prefmem: base: 8100000 size: 8100000 align: 27 gran: 20 limit: ffffffff done
PCI: 00:18.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 00:01.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 01:05.0 24 * [0x0 - 0xfffff] mem
PCI: 01:05.0 18 * [0x100000 - 0x10ffff] mem
PCI: 00:01.0 mem: base: 110000 size: 200000 align: 20 gran: 20 limit: ffffffff done
PCI: 00:0a.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 03:00.0 30 * [0x0 - 0x1ffff] mem
PCI: 00:0a.0 mem: base: 20000 size: 100000 align: 20 gran: 20 limit: ffffffff done
PCI: 00:14.4 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 04:05.0 14 * [0x0 - 0xff] mem
PCI: 00:14.4 mem: base: 100 size: 100000 align: 20 gran: 20 limit: ffffffff done
PCI: 00:01.0 20 * [0x0 - 0x1fffff] mem
PCI: 00:0a.0 20 * [0x200000 - 0x2fffff] mem
PCI: 00:14.4 20 * [0x300000 - 0x3fffff] mem
PCI: 00:14.2 10 * [0x400000 - 0x403fff] mem
PCI: 00:12.0 10 * [0x404000 - 0x404fff] mem
PCI: 00:12.1 10 * [0x405000 - 0x405fff] mem
PCI: 00:13.0 10 * [0x406000 - 0x406fff] mem
PCI: 00:13.1 10 * [0x407000 - 0x407fff] mem
PCI: 00:14.5 10 * [0x408000 - 0x408fff] mem
PCI: 00:11.0 24 * [0x409000 - 0x4093ff] mem
PCI: 00:12.2 10 * [0x40a000 - 0x40a0ff] mem
PCI: 00:13.2 10 * [0x40b000 - 0x40b0ff] mem
PCI: 00:14.3 a0 * [0x40c000 - 0x40c000] mem
PCI: 00:18.0 mem: base: 40c001 size: 500000 align: 20 gran: 20 limit: ffffffff done
PCI: 00:18.0 02 * [0x0 - 0x80fffff] prefmem
PCI: 00:18.3 94 * [0xc000000 - 0xfffffff] mem
PCI: 00:18.0 01 * [0x10000000 - 0x104fffff] mem
DOMAIN: 0000 mem: base: 10500000 size: 10500000 align: 27 gran: 0 limit: ffffffff done
avoid_fixed_resources: DOMAIN: 0000
avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 000007ff
avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff
constrain_resources: PCI: 00:18.0 04 base 000a0000 limit 000bffff mem (fixed)
constrain_resources: PCI: 00:14.0 74 base fec00000 limit fec00fff mem (fixed)
constrain_resources: PCI: 00:14.0 9c base feb00000 limit feb00fff mem (fixed)
constrain_resources: PCI: 00:14.3 10000000 base 00000000 limit 00000fff io (fixed)
constrain_resources: PNP: 002e.2 60 base 000003f8 limit 000003ff io (fixed)
constrain_resources: PNP: 002e.3 60 base 000002f8 limit 000002ff io (fixed)
constrain_resources: PNP: 002e.5 60 base 00000060 limit 00000060 io (fixed)
constrain_resources: PNP: 002e.5 62 base 00000064 limit 00000064 io (fixed)
constrain_resources: PNP: 002e.b 60 base 00000290 limit 00000291 io (fixed)
avoid_fixed_resources:@DOMAIN: 0000 10000000 base 00000065 limit 0000028f
avoid_fixed_resources:@DOMAIN: 0000 10000100 base e8000000 limit feafffff
Setting resources...
DOMAIN: 0000 io: base:65 size:4000 align:12 gran:0 limit:28f
!! Resource didn't fit !!
aligned base 1000 size 4000 limit 28f
4fff needs to be <= 28f (limit)
PCI: 00:18.0 00 * [0x0 - 0x3fff] io
PCI: 00:18.0 00 * [0x0 - 0x3fff] io
DOMAIN: 0000 io: next_base: 65 size: 4000 align: 12 gran: 0 done
PCI: 00:18.0 io: base:0 size:4000 align:12 gran:12 limit:28f
!! Resource didn't fit !!
aligned base 0 size 1000 limit 28f
fff needs to be <= 28f (limit)
PCI: 00:01.0 1c * [0x0 - 0xfff] io
PCI: 00:01.0 1c * [0x0 - 0xfff] io
!! Resource didn't fit !!
aligned base 0 size 1000 limit 28f
fff needs to be <= 28f (limit)
PCI: 00:0a.0 1c * [0x1000 - 0x1fff] io
PCI: 00:0a.0 1c * [0x1000 - 0x1fff] io
!! Resource didn't fit !!
aligned base 0 size 1000 limit 28f
fff needs to be <= 28f (limit)
PCI: 00:14.4 1c * [0x2000 - 0x2fff] io
PCI: 00:14.4 1c * [0x2000 - 0x2fff] io
PCI: 00:11.0 20 * [0x0 - 0xf] io
PCI: 00:14.1 20 * [0x10 - 0x1f] io
PCI: 00:11.0 10 * [0x20 - 0x27] io
PCI: 00:11.0 18 * [0x28 - 0x2f] io
PCI: 00:14.1 10 * [0x30 - 0x37] io
PCI: 00:14.1 18 * [0x38 - 0x3f] io
PNP: 002e.6 62 * [0x40 - 0x47] io
PCI: 00:11.0 14 * [0x48 - 0x4b] io
PCI: 00:11.0 1c * [0x4c - 0x4f] io
PCI: 00:14.1 14 * [0x50 - 0x53] io
PCI: 00:14.1 1c * [0x54 - 0x57] io
PCI: 00:18.0 io: next_base: 58 size: 4000 align: 12 gran: 12 done
PCI: 00:01.0 io: base:0 size:1000 align:12 gran:12 limit:28f
PCI: 01:05.0 14 * [0x0 - 0xff] io
PCI: 00:01.0 io: next_base: 100 size: 1000 align: 12 gran: 12 done
PCI: 00:0a.0 io: base:1000 size:1000 align:12 gran:12 limit:28f
!! Resource didn't fit !!
aligned base 1000 size 100 limit 28f
10ff needs to be <= 28f (limit)
PCI: 03:00.0 10 * [0x0 - 0xff] io
PCI: 03:00.0 10 * [0x0 - 0xff] io
PCI: 00:0a.0 io: next_base: 1000 size: 1000 align: 12 gran: 12 done
PCI: 00:14.4 io: base:2000 size:1000 align:12 gran:12 limit:28f
!! Resource didn't fit !!
aligned base 2000 size 100 limit 28f
20ff needs to be <= 28f (limit)
PCI: 04:05.0 10 * [0x0 - 0xff] io
PCI: 04:05.0 10 * [0x0 - 0xff] io
PCI: 00:14.4 io: next_base: 2000 size: 1000 align: 12 gran: 12 done
DOMAIN: 0000 mem: base:e8000000 size:10500000 align:27 gran:0 limit:feafffff
PCI: 00:18.0 02 * [0xe8000000 - 0xf00fffff] prefmem
PCI: 00:18.3 94 * [0xf4000000 - 0xf7ffffff] mem
PCI: 00:18.0 01 * [0xf8000000 - 0xf84fffff] mem
DOMAIN: 0000 mem: next_base: f8500000 size: 10500000 align: 27 gran: 0 done
PCI: 00:18.0 prefmem: base:e8000000 size:8100000 align:27 gran:20 limit:f00fffff
PCI: 00:01.0 24 * [0xe8000000 - 0xefffffff] prefmem
PCI: 00:0a.0 24 * [0xf0000000 - 0xf00fffff] prefmem
PCI: 00:18.0 prefmem: next_base: f0100000 size: 8100000 align: 27 gran: 20 done
PCI: 00:01.0 prefmem: base:e8000000 size:8000000 align:27 gran:20 limit:efffffff
PCI: 01:05.0 10 * [0xe8000000 - 0xefffffff] prefmem
PCI: 00:01.0 prefmem: next_base: f0000000 size: 8000000 align: 27 gran: 20 done
PCI: 00:0a.0 prefmem: base:f0000000 size:100000 align:20 gran:20 limit:f00fffff
PCI: 03:00.0 20 * [0xf0000000 - 0xf0003fff] prefmem
PCI: 03:00.0 18 * [0xf0004000 - 0xf0004fff] prefmem
PCI: 00:0a.0 prefmem: next_base: f0005000 size: 100000 align: 20 gran: 20 done
PCI: 00:14.4 prefmem: base:f00fffff size:0 align:20 gran:20 limit:f00fffff
PCI: 00:14.4 prefmem: next_base: f00fffff size: 0 align: 20 gran: 20 done
PCI: 00:18.0 mem: base:f8000000 size:500000 align:20 gran:20 limit:f84fffff
PCI: 00:01.0 20 * [0xf8000000 - 0xf81fffff] mem
PCI: 00:0a.0 20 * [0xf8200000 - 0xf82fffff] mem
PCI: 00:14.4 20 * [0xf8300000 - 0xf83fffff] mem
PCI: 00:14.2 10 * [0xf8400000 - 0xf8403fff] mem
PCI: 00:12.0 10 * [0xf8404000 - 0xf8404fff] mem
PCI: 00:12.1 10 * [0xf8405000 - 0xf8405fff] mem
PCI: 00:13.0 10 * [0xf8406000 - 0xf8406fff] mem
PCI: 00:13.1 10 * [0xf8407000 - 0xf8407fff] mem
PCI: 00:14.5 10 * [0xf8408000 - 0xf8408fff] mem
PCI: 00:11.0 24 * [0xf8409000 - 0xf84093ff] mem
PCI: 00:12.2 10 * [0xf840a000 - 0xf840a0ff] mem
PCI: 00:13.2 10 * [0xf840b000 - 0xf840b0ff] mem
PCI: 00:14.3 a0 * [0xf840c000 - 0xf840c000] mem
PCI: 00:18.0 mem: next_base: f840c001 size: 500000 align: 20 gran: 20 done
PCI: 00:01.0 mem: base:f8000000 size:200000 align:20 gran:20 limit:f81fffff
PCI: 01:05.0 24 * [0xf8000000 - 0xf80fffff] mem
PCI: 01:05.0 18 * [0xf8100000 - 0xf810ffff] mem
PCI: 00:01.0 mem: next_base: f8110000 size: 200000 align: 20 gran: 20 done
PCI: 00:0a.0 mem: base:f8200000 size:100000 align:20 gran:20 limit:f82fffff
PCI: 03:00.0 30 * [0xf8200000 - 0xf821ffff] mem
PCI: 00:0a.0 mem: next_base: f8220000 size: 100000 align: 20 gran: 20 done
PCI: 00:14.4 mem: base:f8300000 size:100000 align:20 gran:20 limit:f83fffff
PCI: 04:05.0 14 * [0xf8300000 - 0xf83000ff] mem
PCI: 00:14.4 mem: next_base: f8300100 size: 100000 align: 20 gran: 20 done
Root Device assign_resources, bus 0 link: 0
node 0 : uma_memory_base/1024=0x00060000, mmio_basek=0x003a0000, basek=0x00000300, limitk=0x00080000
node 0: UMA memory starts below mmio_basek
0: mmio_basek=003a0000, basek=00000300, limitk=00080000
DOMAIN: 0000 assign_resources, bus 0 link: 0
amdk8_set_resource, enabling legacy VGA IO forwarding for PCI: 00:18.0 link 0x0
PCI: 00:18.0 1c0 <- [0x0000000000 - 0x0000003fff] size 0x00004000 gran 0x0c io <node 0 link 0>
PCI: 00:18.0 1b8 <- [0x00e8000000 - 0x00f00fffff] size 0x08100000 gran 0x14 prefmem <node 0 link 0>
PCI: 00:18.0 1b0 <- [0x00f8000000 - 0x00f84fffff] size 0x00500000 gran 0x14 mem <node 0 link 0>
PCI: 00:18.0 1a8 <- [0x00000a0000 - 0x00000bffff] size 0x00020000 gran 0x00 mem <node 0 link 0>
PCI: 00:18.0 assign_resources, bus 0 link: 0
PCI: 00:01.0 1c <- [0x0000000000 - 0x0000000fff] size 0x00001000 gran 0x0c bus 01 io
PCI: 00:01.0 24 <- [0x00e8000000 - 0x00efffffff] size 0x08000000 gran 0x14 bus 01 prefmem
PCI: 00:01.0 20 <- [0x00f8000000 - 0x00f81fffff] size 0x00200000 gran 0x14 bus 01 mem
PCI: 00:01.0 assign_resources, bus 1 link: 0
PCI: 01:05.0 10 <- [0x00e8000000 - 0x00efffffff] size 0x08000000 gran 0x1b prefmem
PCI: 01:05.0 14 <- [0x0000000000 - 0x00000000ff] size 0x00000100 gran 0x08 io
PCI: 01:05.0 18 <- [0x00f8100000 - 0x00f810ffff] size 0x00010000 gran 0x10 mem
PCI: 01:05.0 24 <- [0x00f8000000 - 0x00f80fffff] size 0x00100000 gran 0x14 mem
PCI: 00:01.0 assign_resources, bus 1 link: 0
PCI: 00:0a.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 03 io
PCI: 00:0a.0 24 <- [0x00f0000000 - 0x00f00fffff] size 0x00100000 gran 0x14 bus 03 prefmem
PCI: 00:0a.0 20 <- [0x00f8200000 - 0x00f82fffff] size 0x00100000 gran 0x14 bus 03 mem
PCI: 00:0a.0 assign_resources, bus 3 link: 0
ERROR: PCI: 03:00.0 10 io size: 0x0000000100 not assigned
PCI: 03:00.0 18 <- [0x00f0004000 - 0x00f0004fff] size 0x00001000 gran 0x0c prefmem64
PCI: 03:00.0 20 <- [0x00f0000000 - 0x00f0003fff] size 0x00004000 gran 0x0e prefmem64
PCI: 03:00.0 30 <- [0x00f8200000 - 0x00f821ffff] size 0x00020000 gran 0x11 romem
PCI: 00:0a.0 assign_resources, bus 3 link: 0
PCI: 00:11.0 10 <- [0x0000000020 - 0x0000000027] size 0x00000008 gran 0x03 io
PCI: 00:11.0 14 <- [0x0000000048 - 0x000000004b] size 0x00000004 gran 0x02 io
PCI: 00:11.0 18 <- [0x0000000028 - 0x000000002f] size 0x00000008 gran 0x03 io
PCI: 00:11.0 1c <- [0x000000004c - 0x000000004f] size 0x00000004 gran 0x02 io
PCI: 00:11.0 20 <- [0x0000000000 - 0x000000000f] size 0x00000010 gran 0x04 io
PCI: 00:11.0 24 <- [0x00f8409000 - 0x00f84093ff] size 0x00000400 gran 0x0a mem
PCI: 00:12.0 10 <- [0x00f8404000 - 0x00f8404fff] size 0x00001000 gran 0x0c mem
PCI: 00:12.1 10 <- [0x00f8405000 - 0x00f8405fff] size 0x00001000 gran 0x0c mem
PCI: 00:12.2 10 <- [0x00f840a000 - 0x00f840a0ff] size 0x00000100 gran 0x08 mem
PCI: 00:13.0 10 <- [0x00f8406000 - 0x00f8406fff] size 0x00001000 gran 0x0c mem
PCI: 00:13.1 10 <- [0x00f8407000 - 0x00f8407fff] size 0x00001000 gran 0x0c mem
PCI: 00:13.2 10 <- [0x00f840b000 - 0x00f840b0ff] size 0x00000100 gran 0x08 mem
PCI: 00:14.0 assign_resources, bus 1 link: 0
PCI: 00:14.0 assign_resources, bus 1 link: 0
PCI: 00:14.1 10 <- [0x0000000030 - 0x0000000037] size 0x00000008 gran 0x03 io
PCI: 00:14.1 14 <- [0x0000000050 - 0x0000000053] size 0x00000004 gran 0x02 io
PCI: 00:14.1 18 <- [0x0000000038 - 0x000000003f] size 0x00000008 gran 0x03 io
PCI: 00:14.1 1c <- [0x0000000054 - 0x0000000057] size 0x00000004 gran 0x02 io
PCI: 00:14.1 20 <- [0x0000000010 - 0x000000001f] size 0x00000010 gran 0x04 io
PCI: 00:14.2 10 <- [0x00f8400000 - 0x00f8403fff] size 0x00004000 gran 0x0e mem64
PCI: 00:14.3 a0 <- [0x00f840c000 - 0x00f840c000] size 0x00000001 gran 0x00 mem
PCI: 00:14.3 assign_resources, bus 0 link: 0
PNP: 002e.2 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io
PNP: 002e.2 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq
PNP: 002e.3 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io
PNP: 002e.3 70 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 irq
PNP: 002e.5 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io
PNP: 002e.5 62 <- [0x0000000064 - 0x0000000064] size 0x00000001 gran 0x00 io
PNP: 002e.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq
ERROR: PNP: 002e.5 72 irq size: 0x0000000001 not assigned
PNP: 002e.b 60 <- [0x0000000290 - 0x0000000291] size 0x00000002 gran 0x01 io
ERROR: PNP: 002e.b 70 irq size: 0x0000000001 not assigned
PNP: 002e.6 62 <- [0x0000000040 - 0x0000000047] size 0x00000008 gran 0x03 io
PCI: 00:14.3 assign_resources, bus 0 link: 0
PCI: 00:14.4 1c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x0c bus 04 io
PCI: 00:14.4 24 <- [0x00f00fffff - 0x00f00ffffe] size 0x00000000 gran 0x14 bus 04 prefmem
PCI: 00:14.4 20 <- [0x00f8300000 - 0x00f83fffff] size 0x00100000 gran 0x14 bus 04 mem
PCI: 00:14.4 assign_resources, bus 4 link: 0
ERROR: PCI: 04:05.0 10 io size: 0x0000000100 not assigned
PCI: 04:05.0 14 <- [0x00f8300000 - 0x00f83000ff] size 0x00000100 gran 0x08 mem
PCI: 00:14.4 assign_resources, bus 4 link: 0
PCI: 00:14.5 10 <- [0x00f8408000 - 0x00f8408fff] size 0x00001000 gran 0x0c mem
PCI: 00:18.0 assign_resources, bus 0 link: 0
PCI: 00:18.3 94 <- [0x00f4000000 - 0x00f7ffffff] size 0x04000000 gran 0x1a mem <gart>
DOMAIN: 0000 assign_resources, bus 0 link: 0
Root Device assign_resources, bus 0 link: 0
Done setting resources.
Show resources in subtree (Root Device)...After assigning values.
Root Device child on link 0 CPU_CLUSTER: 0
CPU_CLUSTER: 0 child on link 0 APIC: 00
APIC: 00
DOMAIN: 0000 child on link 0 PCI: 00:18.0
DOMAIN: 0000 resource base 65 size 4000 align 12 gran 0 limit 28f flags 40040100 index 10000000
DOMAIN: 0000 resource base e8000000 size 10500000 align 27 gran 0 limit feafffff flags 40040200 index 10000100
DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 10
DOMAIN: 0000 resource base c0000 size 1ff40000 align 0 gran 0 limit 0 flags e0004200 index 20
DOMAIN: 0000 resource base 18000000 size 8000000 align 0 gran 0 limit 0 flags f0000200 index 7
PCI: 00:18.0 child on link 0 PCI: 00:00.0
PCI: 00:18.0 resource base 0 size 4000 align 12 gran 12 limit 28f flags 60080100 index 1c0
PCI: 00:18.0 resource base e8000000 size 8100000 align 27 gran 20 limit f00fffff flags 60081200 index 1b8
PCI: 00:18.0 resource base f8000000 size 500000 align 20 gran 20 limit f84fffff flags 60080200 index 1b0
PCI: 00:18.0 resource base a0000 size 20000 align 0 gran 0 limit ffffffff flags e0000200 index 1a8
PCI: 00:00.0
PCI: 00:01.0 child on link 0 PCI: 01:05.0
PCI: 00:01.0 resource base 0 size 1000 align 12 gran 12 limit 28f flags 60080102 index 1c
PCI: 00:01.0 resource base e8000000 size 8000000 align 27 gran 20 limit efffffff flags 60081202 index 24
PCI: 00:01.0 resource base f8000000 size 200000 align 20 gran 20 limit f81fffff flags 60080202 index 20
PCI: 01:05.0
PCI: 01:05.0 resource base e8000000 size 8000000 align 27 gran 27 limit efffffff flags 60001200 index 10
PCI: 01:05.0 resource base 0 size 100 align 8 gran 8 limit ff flags 60000100 index 14
PCI: 01:05.0 resource base f8100000 size 10000 align 16 gran 16 limit f810ffff flags 60000200 index 18
PCI: 01:05.0 resource base f8000000 size 100000 align 20 gran 20 limit f80fffff flags 60000200 index 24
PCI: 00:02.0
PCI: 00:03.0
PCI: 00:04.0
PCI: 00:05.0
PCI: 00:06.0
PCI: 00:07.0
PCI: 00:08.0
PCI: 00:09.0
PCI: 00:0a.0 child on link 0 PCI: 03:00.0
PCI: 00:0a.0 resource base 1000 size 1000 align 12 gran 12 limit 28f flags 60080102 index 1c
PCI: 00:0a.0 resource base f0000000 size 100000 align 20 gran 20 limit f00fffff flags 60081202 index 24
PCI: 00:0a.0 resource base f8200000 size 100000 align 20 gran 20 limit f82fffff flags 60080202 index 20
PCI: 03:00.0
PCI: 03:00.0 resource base 0 size 100 align 8 gran 8 limit 28f flags 100 index 10
PCI: 03:00.0 resource base f0004000 size 1000 align 12 gran 12 limit f0004fff flags 60001201 index 18
PCI: 03:00.0 resource base f0000000 size 4000 align 14 gran 14 limit f0003fff flags 60001201 index 20
PCI: 03:00.0 resource base f8200000 size 20000 align 17 gran 17 limit f821ffff flags 60002200 index 30
PCI: 00:11.0
PCI: 00:11.0 resource base 20 size 8 align 3 gran 3 limit 27 flags 60000100 index 10
PCI: 00:11.0 resource base 48 size 4 align 2 gran 2 limit 4b flags 60000100 index 14
PCI: 00:11.0 resource base 28 size 8 align 3 gran 3 limit 2f flags 60000100 index 18
PCI: 00:11.0 resource base 4c size 4 align 2 gran 2 limit 4f flags 60000100 index 1c
PCI: 00:11.0 resource base 0 size 10 align 4 gran 4 limit f flags 60000100 index 20
PCI: 00:11.0 resource base f8409000 size 400 align 12 gran 10 limit f84093ff flags 60000200 index 24
PCI: 00:12.0
PCI: 00:12.0 resource base f8404000 size 1000 align 12 gran 12 limit f8404fff flags 60000200 index 10
PCI: 00:12.1
PCI: 00:12.1 resource base f8405000 size 1000 align 12 gran 12 limit f8405fff flags 60000200 index 10
PCI: 00:12.2
PCI: 00:12.2 resource base f840a000 size 100 align 12 gran 8 limit f840a0ff flags 60000200 index 10
PCI: 00:13.0
PCI: 00:13.0 resource base f8406000 size 1000 align 12 gran 12 limit f8406fff flags 60000200 index 10
PCI: 00:13.1
PCI: 00:13.1 resource base f8407000 size 1000 align 12 gran 12 limit f8407fff flags 60000200 index 10
PCI: 00:13.2
PCI: 00:13.2 resource base f840b000 size 100 align 12 gran 8 limit f840b0ff flags 60000200 index 10
PCI: 00:14.0 child on link 0 I2C: 01:50
PCI: 00:14.0 resource base fec00000 size 1000 align 8 gran 8 limit ffffffff flags d0000200 index 74
PCI: 00:14.0 resource base feb00000 size 1000 align 8 gran 8 limit ffffffff flags d0000200 index 9c
PCI: 00:14.0 resource base fed00000 size 400 align 8 gran 8 limit ffffffff flags d0000200 index b4
PCI: 00:14.0 resource base b00 size 10 align 8 gran 8 limit ffff flags d0000100 index 90
PCI: 00:14.0 resource base b20 size 10 align 8 gran 8 limit ffff flags d0000100 index 58
I2C: 01:50
I2C: 01:51
I2C: 01:52
I2C: 01:53
PCI: 00:14.1
PCI: 00:14.1 resource base 30 size 8 align 3 gran 3 limit 37 flags 60000100 index 10
PCI: 00:14.1 resource base 50 size 4 align 2 gran 2 limit 53 flags 60000100 index 14
PCI: 00:14.1 resource base 38 size 8 align 3 gran 3 limit 3f flags 60000100 index 18
PCI: 00:14.1 resource base 54 size 4 align 2 gran 2 limit 57 flags 60000100 index 1c
PCI: 00:14.1 resource base 10 size 10 align 4 gran 4 limit 1f flags 60000100 index 20
PCI: 00:14.2
PCI: 00:14.2 resource base f8400000 size 4000 align 14 gran 14 limit f8403fff flags 60000201 index 10
PCI: 00:14.3 child on link 0 PNP: 002e.0
PCI: 00:14.3 resource base f840c000 size 1 align 12 gran 0 limit f840c000 flags 60000200 index a0
PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
PNP: 002e.0
PNP: 002e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
PNP: 002e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
PNP: 002e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags c0000800 index 74
PNP: 002e.1
PNP: 002e.1 resource base 378 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
PNP: 002e.1 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
PNP: 002e.2
PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60
PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
PNP: 002e.3
PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60
PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
PNP: 002e.5
PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 60
PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 62
PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
PNP: 002e.5 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 72
PNP: 002e.307
PNP: 002e.8
PNP: 002e.9
PNP: 002e.109
PNP: 002e.209
PNP: 002e.309
PNP: 002e.a
PNP: 002e.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
PNP: 002e.b
PNP: 002e.b resource base 290 size 2 align 1 gran 1 limit 7ff flags e0000100 index 60
PNP: 002e.b resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
PNP: 002e.c
PNP: 002e.6
PNP: 002e.6 resource base 40 size 8 align 3 gran 3 limit 47 flags 60000100 index 62
PCI: 00:14.4 child on link 0 PCI: 04:05.0
PCI: 00:14.4 resource base 2000 size 1000 align 12 gran 12 limit 28f flags 60080102 index 1c
PCI: 00:14.4 resource base f00fffff size 0 align 20 gran 20 limit f00fffff flags 60081202 index 24
PCI: 00:14.4 resource base f8300000 size 100000 align 20 gran 20 limit f83fffff flags 60080202 index 20
PCI: 04:05.0
PCI: 04:05.0 resource base 0 size 100 align 8 gran 8 limit 28f flags 100 index 10
PCI: 04:05.0 resource base f8300000 size 100 align 12 gran 8 limit f83000ff flags 60000200 index 14
PCI: 00:14.5
PCI: 00:14.5 resource base f8408000 size 1000 align 12 gran 12 limit f8408fff flags 60000200 index 10
PCI: 00:18.1
PCI: 00:18.2
PCI: 00:18.3
PCI: 00:18.3 resource base f4000000 size 4000000 align 26 gran 26 limit f7ffffff flags 60000200 index 94
Done allocating resources.
Enabling resources...
PCI: 00:18.0 cmd <- 00
PCI: 00:18.1 subsystem <- 1022/3060
PCI: 00:18.1 cmd <- 00
PCI: 00:18.2 subsystem <- 1022/3060
PCI: 00:18.2 cmd <- 00
PCI: 00:18.3 cmd <- 00
PCI: 00:00.0 subsystem <- 1022/3060
PCI: 00:00.0 cmd <- 06
PCI: 00:01.0 bridge ctrl <- 000b
PCI: 00:01.0 cmd <- 074.7
coreboot-4.7 Mon Jan 15 00:44:43 UTC 2018 romstage starting...
bsp_apicid=0x0
Enabling routing table for node 0 done.
Enabling SMP settings
01 nodes initialized.
Enabling UP settings
Disabling read/write/fill probes for UP... done.
NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead.
coherent_ht_finalize
done
core0 started:
NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead.
NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead.
SBLink=00
NC node|link=00
rs780_early_setup()
k8_optimization()
rs780_por_init
sb700_early_setup()
sb700_devices_por_init()
sb700_devices_por_init(): SMBus Device, BDF:0-20-0
SMBus controller enabled, sb revision is A14
sb700_devices_por_init(): IDE Device, BDF:0-20-1
sb700_devices_por_init(): LPC Device, BDF:0-20-3
sb700_devices_por_init(): P2P Bridge, BDF:0-20-4
sb700_devices_por_init(): SATA Device, BDF:0-17-0
sb700_pmio_por_init()
begin msr fid, vid: hi=0x12040606, lo=0x40a0a0a
NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead.
Current fid_cur: 0xa, fid_max: 0xa
Requested fid_new: 0xa
end msr fid, vid: hi=0x12040604, lo=0x40a0a0a
entering optimize_link_incoherent_ht
sysinfo->link_pair_num=0x1
entering ht_optimize_link
pos=0x8a, unfiltered freq_cap=0x8075
pos=0x8a, filtered freq_cap=0x75
pos=0xd2, unfiltered freq_cap=0x1e75
pos=0xd2, filtered freq_cap=0x1e75
freq_cap1=0x75, freq_cap2=0x1e75
dev1 old_freq=0x0, freq=0x6, needs_reset=0x1
dev2 old_freq=0x0, freq=0x6, needs_reset=0x1
width_cap1=0x11, width_cap2=0x11
dev1 input ln_width1=0x4, ln_width2=0x4
dev1 input width=0x1
dev1 output ln_width1=0x4, ln_width2=0x4
dev1 input|output width=0x11
old dev1 input|output width=0x11
dev2 input|output width=0x11
old dev2 input|output width=0x11
after ht_optimize_link for link pair 0, reset_needed=0x1
after optimize_link_read_pointers_chain, reset_needed=0x1
rs780_htinit cpu_ht_freq=6.
rs780_htinit: HT1 mode
needs_reset=0x1
ht reset -
soft_reset() called!
coreboot-4.7 Mon Jan 15 00:44:43 UTC 2018 romstage starting...
bsp_apicid=0x0
Enabling routing table for node 0 done.
Enabling SMP settings
01 nodes initialized.
Enabling UP settings
Disabling read/write/fill probes for UP... done.
NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead.
coherent_ht_finalize
done
core0 started:
NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead.
NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead.
SBLink=00
NC node|link=00
rs780_early_setup()
k8_optimization()
rs780_por_init
sb700_early_setup()
sb700_devices_por_init()
sb700_devices_por_init(): SMBus Device, BDF:0-20-0
SMBus controller enabled, sb revision is A14
sb700_devices_por_init(): IDE Device, BDF:0-20-1
sb700_devices_por_init(): LPC Device, BDF:0-20-3
sb700_devices_por_init(): P2P Bridge, BDF:0-20-4
sb700_devices_por_init(): SATA Device, BDF:0-17-0
sb700_pmio_por_init()
begin msr fid, vid: hi=0x12040604, lo=0x40a0a0a
NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead.
end msr fid, vid: hi=0x12040604, lo=0x40a0a0a
entering optimize_link_incoherent_ht
sysinfo->link_pair_num=0x1
entering ht_optimize_link
pos=0x8a, unfiltered freq_cap=0x8075
pos=0x8a, filtered freq_cap=0x75
pos=0xd2, unfiltered freq_cap=0x1e75
pos=0xd2, filtered freq_cap=0x1e75
freq_cap1=0x75, freq_cap2=0x1e75
dev1 old_freq=0x6, freq=0x6, needs_reset=0x0
dev2 old_freq=0x6, freq=0x6, needs_reset=0x0
width_cap1=0x11, width_cap2=0x11
dev1 input ln_width1=0x4, ln_width2=0x4
dev1 input width=0x1
dev1 output ln_width1=0x4, ln_width2=0x4
dev1 input|output width=0x11
old dev1 input|output width=0x11
dev2 input|output width=0x11
old dev2 input|output width=0x11
after ht_optimize_link for link pair 0, reset_needed=0x0
after optimize_link_read_pointers_chain, reset_needed=0x0
rs780_htinit cpu_ht_freq=6.
rs780_htinit: HT1 mode
needs_reset=0x0
sysinfo->nodes: 1 sysinfo->ctrl: 000c8128 spd_addr: fff0b1dc
Ram1.00
setting up CPU00 northbridge registers
done.
Ram2.00
NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead.
Unbuffered
NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead.
Setting DualDIMMen
200MHz
NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead.
RAM end at 0x00080000 kB
Lower RAM end at 0x00080000 kB
Ram3
Initializing memory: done
Handling memory hole at 0x00300000 (default)
Ram4
BSP overran lower stack boundary. Undefined behaviour may result!
Romstage handoff structure not added!
CBFS: 'Master Header Locator' located CBFS at [100:fffc0)
CBFS: Locating 'fallback/ramstage'
CBFS: Found @ offset d300 size 10302
coreboot-4.7 Mon Jan 15 00:44:43 UTC 2018 ramstage starting...
Normal boot.
Enumerating buses...
Show all devs... Before device enumeration.
Root Device: enabled 1
CPU_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
DOMAIN: 0000: enabled 1
PCI: 00:18.0: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:02.0: enabled 1
PCI: 00:03.0: enabled 0
PCI: 00:04.0: enabled 0
PCI: 00:05.0: enabled 0
PCI: 00:06.0: enabled 0
PCI: 00:07.0: enabled 0
PCI: 00:08.0: enabled 0
PCI: 00:09.0: enabled 1
PCI: 00:0a.0: enabled 1
PCI: 00:11.0: enabled 1
PCI: 00:12.0: enabled 1
PCI: 00:12.1: enabled 1
PCI: 00:12.2: enabled 1
PCI: 00:13.0: enabled 1
PCI: 00:13.1: enabled 1
PCI: 00:13.2: enabled 1
PCI: 00:14.0: enabled 1
I2C: 00:50: enabled 1
I2C: 00:51: enabled 1
I2C: 00:52: enabled 1
I2C: 00:53: enabled 1
PCI: 00:14.1: enabled 1
PCI: 00:14.2: enabled 1
PCI: 00:14.3: enabled 1
PNP: 002e.0: enabled 0
PNP: 002e.1: enabled 0
PNP: 002e.2: enabled 1
PNP: 002e.3: enabled 1
PNP: 002e.5: enabled 1
PNP: 002e.307: enabled 0
PNP: 002e.8: enabled 1
PNP: 002e.9: enabled 1
PNP: 002e.109: enabled 1
PNP: 002e.209: enabled 1
PNP: 002e.309: enabled 0
PNP: 002e.a: enabled 0
PNP: 002e.b: enabled 1
PNP: 002e.c: enabled 0
PCI: 00:14.4: enabled 1
PCI: 00:14.5: enabled 1
PCI: 00:18.1: enabled 1
PCI: 00:18.2: enabled 1
PCI: 00:18.3: enabled 1
Compare with tree...
Root Device: enabled 1
CPU_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
DOMAIN: 0000: enabled 1
PCI: 00:18.0: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:02.0: enabled 1
PCI: 00:03.0: enabled 0
PCI: 00:04.0: enabled 0
PCI: 00:05.0: enabled 0
PCI: 00:06.0: enabled 0
PCI: 00:07.0: enabled 0
PCI: 00:08.0: enabled 0
PCI: 00:09.0: enabled 1
PCI: 00:0a.0: enabled 1
PCI: 00:11.0: enabled 1
PCI: 00:12.0: enabled 1
PCI: 00:12.1: enabled 1
PCI: 00:12.2: enabled 1
PCI: 00:13.0: enabled 1
PCI: 00:13.1: enabled 1
PCI: 00:13.2: enabled 1
PCI: 00:14.0: enabled 1
I2C: 00:50: enabled 1
I2C: 00:51: enabled 1
I2C: 00:52: enabled 1
I2C: 00:53: enabled 1
PCI: 00:14.1: enabled 1
PCI: 00:14.2: enabled 1
PCI: 00:14.3: enabled 1
PNP: 002e.0: enabled 0
PNP: 002e.1: enabled 0
PNP: 002e.2: enabled 1
PNP: 002e.3: enabled 1
PNP: 002e.5: enabled 1
PNP: 002e.307: enabled 0
PNP: 002e.8: enabled 1
PNP: 002e.9: enabled 1
PNP: 002e.109: enabled 1
PNP: 002e.209: enabled 1
PNP: 002e.309: enabled 0
PNP: 002e.a: enabled 0
PNP: 002e.b: enabled 1
PNP: 002e.c: enabled 0
PCI: 00:14.4: enabled 1
PCI: 00:14.5: enabled 1
PCI: 00:18.1: enabled 1
PCI: 00:18.2: enabled 1
PCI: 00:18.3: enabled 1
Mainboard 939A785GMH/128M Enable. dev=0x0011fea0
Root Device scanning...
root_dev_scan_bus for Root Device
setup_bsp_ramtop, TOP MEM: msr.lo = 0x20000000, msr.hi = 0x00000000
setup_bsp_ramtop, TOP MEM2: msr.lo = 0x00000000, msr.hi = 0x00000000
setup_uma_memory: uma size 0x08000000, memory start 0x18000000
CPU_CLUSTER: 0 enabled
DOMAIN: 0000 enabled
CPU_CLUSTER: 0 scanning...
PCI: 00:18.3 siblings=0
Found Rev E or Rev F later single core
CPU: APIC: 00 enabled
scan_bus: scanning of bus CPU_CLUSTER: 0 took 0 usecs
DOMAIN: 0000 scanning...
PCI: pci_scan_bus for bus 00
PCI: 00:18.0 [1022/1100] bus ops
PCI: 00:18.0 [1022/1100] enabled
PCI: 00:18.1 [1022/1101] enabled
PCI: 00:18.2 [1022/1102] enabled
PCI: 00:18.3 [1022/1103] ops
PCI: 00:18.3 [1022/1103] enabled
PCI: 00:18.0 scanning...
do_hypertransport_scan_chain for bus 00
rs780_enable: dev=00121bc0, VID_DID=0x96011022
Bus-0, Dev-0, Fun-0.
enable_pcie_bar3()
gpp_sb_init nb_dev=0x0, dev=0x40, port=0x8
NB_PCI_REG04 = 6.
NB_PCI_REG84 = 3000095.
NB_PCI_REG4C = 52042.
PCI: 00:00.0 [1022/9601] enabled
Capability: type 0x08 @ 0xc4
flags: 0x0180
PCI: 00:00.0 count: 000c static_count: 0015
PCI: 00:00.0 [1022/9601] enabled next_unitid: 0015
PCI: pci_scan_bus for bus 00
rs780_enable: dev=00121bc0, VID_DID=0x96011022
Bus-0, Dev-0, Fun-0.
enable_pcie_bar3()
gpp_sb_init nb_dev=0x0, dev=0x40, port=0x8
NB_PCI_REG04 = 6.
NB_PCI_REG84 = 3000095.
NB_PCI_REG4C = 52042.
PCI: 00:00.0 [1022/9601] enabled
rs780_enable: dev=00121b20, VID_DID=0x96021022
Bus-0, Dev-1, Fun-0.
GC is accessible from now on.
Capability: type 0x08 @ 0x44
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0x44
Capability: type 0x08 @ 0x44
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0x44
Capability: type 0x0d @ 0xb0
PCI: 00:01.0 [1022/9602] enabled
rs780_enable: dev=00121a80, VID_DID=0x96031022
Bus-0, Dev-2,3, Fun-0. enable=1
rs780_gfx_init, nb_dev=0x00121bc0, dev=0x00121a80, port=0x2.
misc 28 = 1
rs780_gfx_init step5.9.12.1.
rs780_gfx_init step5.9.12.3.
rs780_gfx_init step5.9.12.9.
rs780_gfx_init step1.
device = 2
rs780_gfx_init single_port_configuration.
PcieLinkTraining port=2:lc current state=2030400
rs780_gfx_init single_port_configuration step12.
rs780_gfx_init single_port_configuration step13.
rs780_gfx_init single_port_configuration step14.
PCI: Static device PCI: 00:02.0 not found, disabling it.
rs780_enable: dev=001219e0, VID_DID=0xffffffff
Bus-0, Dev-2,3, Fun-0. enable=0
rs780_enable: dev=00121940, VID_DID=0xffffffff
Bus-0, Dev-4,5,6,7, Fun-0. enable=0
rs780_enable: dev=001218a0, VID_DID=0xffffffff
Bus-0, Dev-4,5,6,7, Fun-0. enable=0
rs780_enable: dev=00121800, VID_DID=0xffffffff
Bus-0, Dev-4,5,6,7, Fun-0. enable=0
rs780_enable: dev=00121760, VID_DID=0xffffffff
Bus-0, Dev-4,5,6,7, Fun-0. enable=0
rs780_enable: dev=001216c0, VID_DID=0x960a1022
Bus-0, Dev-8, Fun-0. enable=0
rs780_enable: dev=00121620, VID_DID=0x96081022
Bus-0, Dev-9, 10, Fun-0. enable=1
gpp_sb_init nb_dev=0x0, dev=0x48, port=0x9
PcieLinkTraining port=9:lc current state=10203
PcieTrainPort port=0x9 result=0
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
PCI: 00:09.0 subordinate bus PCI Express
PCI: 00:09.0 [1022/9608] enabled
rs780_enable: dev=00121580, VID_DID=0x96091022
Bus-0, Dev-9, 10, Fun-0. enable=1
gpp_sb_init nb_dev=0x0, dev=0x50, port=0xa
PcieLinkTraining port=a:lc current state=a0b0f10
addr=e0000000,bus=0,devfn=50
PcieTrainPort reg=0x10000
PcieTrainPort port=0xa result=1
disable_pcie_bar3()
rs780 unused GPP ports bitmap=0x2fc, force disabled
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
PCI: 00:0a.0 subordinate bus PCI Express
PCI: 00:0a.0 [1022/9609] enabled
sb7xx_51xx_enable()
PCI: 00:11.0 [1002/4390] ops
PCI: 00:11.0 [1002/4390] enabled
sb7xx_51xx_enable()
PCI: 00:12.0 [1002/4397] ops
PCI: 00:12.0 [1002/4397] enabled
sb7xx_51xx_enable()
PCI: 00:12.1 [1002/4398] ops
PCI: 00:12.1 [1002/4398] enabled
sb7xx_51xx_enable()
PCI: 00:12.2 [1002/4396] ops
PCI: 00:12.2 [1002/4396] enabled
sb7xx_51xx_enable()
PCI: 00:13.0 [1002/4397] ops
PCI: 00:13.0 [1002/4397] enabled
sb7xx_51xx_enable()
PCI: 00:13.1 [1002/4398] ops
PCI: 00:13.1 [1002/4398] enabled
sb7xx_51xx_enable()
PCI: 00:13.2 [1002/4396] ops
PCI: 00:13.2 [1002/4396] enabled
sb7xx_51xx_enable()
PCI: 00:14.0 [1002/4385] bus ops
PCI: 00:14.0 [1002/4385] enabled
sb7xx_51xx_enable()
PCI: 00:14.1 [1002/439c] ops
PCI: 00:14.1 [1002/439c] enabled
sb7xx_51xx_enable()
PCI: 00:14.2 [1002/4383] ops
PCI: 00:14.2 [1002/4383] enabled
sb7xx_51xx_enable()
PCI: 00:14.3 [1002/439d] bus ops
PCI: 00:14.3 [1002/439d] enabled
sb7xx_51xx_enable()
PCI: 00:14.4 [1002/4384] bus ops
PCI: 00:14.4 [1002/4384] enabled
sb7xx_51xx_enable()
PCI: 00:14.5 [1002/4399] ops
PCI: 00:14.5 [1002/4399] enabled
PCI: 00:01.0 scanning...
do_pci_scan_bridge for PCI: 00:01.0
PCI: pci_scan_bus for bus 01
PCI: 01:05.0 [1002/0000] ops
rs780_internal_gfx_enable dev = 0x0017a278, nb_dev = 0x00121bc0.
Sysmem TOM = 0_20000000
Sysmem TOM2 = 0_0
PCI: 01:05.0 [1002/9710] enabled
scan_bus: scanning of bus PCI: 00:01.0 took 0 usecs
PCI: 00:09.0 scanning...
do_pci_scan_bridge for PCI: 00:09.0
PCI: pci_scan_bus for bus 02
scan_bus: scanning of bus PCI: 00:09.0 took 0 usecs
PCI: 00:0a.0 scanning...
do_pci_scan_bridge for PCI: 00:0a.0
PCI: pci_scan_bus for bus 03
PCI: 03:00.0 [10ec/8168] enabled
Capability: type 0x01 @ 0x40
Capability: type 0x05 @ 0x50
Capability: type 0x10 @ 0x70
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x01 @ 0x40
Capability: type 0x05 @ 0x50
Capability: type 0x10 @ 0x70
Failed to enable LTR for dev = PCI: 03:00.0
scan_bus: scanning of bus PCI: 00:0a.0 took 0 usecs
PCI: 00:14.0 scanning...
scan_generic_bus for PCI: 00:14.0
bus: PCI: 00:14.0[0]->I2C: 01:50 enabled
bus: PCI: 00:14.0[0]->I2C: 01:51 enabled
bus: PCI: 00:14.0[0]->I2C: 01:52 enabled
bus: PCI: 00:14.0[0]->I2C: 01:53 enabled
scan_generic_bus for PCI: 00:14.0 done
scan_bus: scanning of bus PCI: 00:14.0 took 0 usecs
PCI: 00:14.3 scanning...
scan_lpc_bus for PCI: 00:14.3
PNP: 002e.0 disabled
PNP: 002e.1 disabled
PNP: 002e.2 enabled
PNP: 002e.3 enabled
PNP: 002e.5 enabled
PNP: 002e.307 disabled
PNP: 002e.8 enabled
PNP: 002e.9 enabled
PNP: 002e.109 enabled
PNP: 002e.209 enabled
PNP: 002e.309 disabled
PNP: 002e.a disabled
PNP: 002e.b enabled
PNP: 002e.c disabled
PNP: 002e.6 enabled
scan_lpc_bus for PCI: 00:14.3 done
scan_bus: scanning of bus PCI: 00:14.3 took 0 usecs
PCI: 00:14.4 scanning...
do_pci_scan_bridge for PCI: 00:14.4
PCI: pci_scan_bus for bus 04
PCI: 04:05.0 [10ec/8139] enabled
scan_bus: scanning of bus PCI: 00:14.4 took 0 usecs
scan_bus: scanning of bus PCI: 00:18.0 took 0 usecs
DOMAIN: 0000 passpw: enabled
scan_bus: scanning of bus DOMAIN: 0000 took 0 usecs
root_dev_scan_bus for Root Device done
scan_bus: scanning of bus Root Device took 0 usecs
done
found VGA at PCI: 01:05.0
Setting up VGA for PCI: 01:05.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:01.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:18.0
Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
Allocating resources...
Reading resources...
Root Device read_resources bus 0 link: 0
CPU_CLUSTER: 0 read_resources bus 0 link: 0
CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
DOMAIN: 0000 read_resources bus 0 link: 0
VGA: PCI: 00:18.0 (aka node 0) link 0 has VGA device
PCI: 00:18.0 read_resources bus 0 link: 0
PCI: 00:00.0 register 1c(00000004), read-only ignoring it
PCI: 00:01.0 read_resources bus 1 link: 0
rs780_gfx_read_resources.
PCI: 00:01.0 read_resources bus 1 link: 0 done
PCI: 00:09.0 register 10(ffffffff), read-only ignoring it
PCI: 00:09.0 register 14(ffffffff), read-only ignoring it
PCI: 00:09.0 register 38(ffffffff), read-only ignoring it
PCI: 00:09.0 read_resources bus 2 link: 0
PCI: 00:09.0 read_resources bus 2 link: 0 done
PCI: 00:0a.0 read_resources bus 3 link: 0
PCI: 00:0a.0 read_resources bus 3 link: 0 done
PCI: 00:14.0 read_resources bus 1 link: 0
I2C: 01:50 missing read_resources
I2C: 01:51 missing read_resources
I2C: 01:52 missing read_resources
I2C: 01:53 missing read_resources
PCI: 00:14.0 read_resources bus 1 link: 0 done
PCI: 00:14.3 read_resources bus 0 link: 0
PCI: 00:14.3 read_resources bus 0 link: 0 done
PCI: 00:14.4 read_resources bus 4 link: 0
PCI: 00:14.4 read_resources bus 4 link: 0 done
PCI: 00:18.0 read_resources bus 0 link: 0 done
PCI: 00:18.0 read_resources bus 0 link: 1
PCI: 00:18.0 read_resources bus 0 link: 1 done
PCI: 00:18.0 read_resources bus 0 link: 2
PCI: 00:18.0 read_resources bus 0 link: 2 done
DOMAIN: 0000 read_resources bus 0 link: 0 done
Root Device read_resources bus 0 link: 0 done
Done reading resources.
Show resources in subtree (Root Device)...After reading.
Root Device child on link 0 CPU_CLUSTER: 0
CPU_CLUSTER: 0 child on link 0 APIC: 00
APIC: 00
DOMAIN: 0000 child on link 0 PCI: 00:18.0
DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
PCI: 00:18.0 child on link 0 PCI: 00:00.0
PCI: 00:18.0 resource base 3 size 0 align 0 gran 0 limit 1fff000 flags 1 index 1c0
PCI: 00:18.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80100 index 0
PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 81200 index 2
PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80200 index 1
PCI: 00:18.0 resource base a0000 size 20000 align 0 gran 0 limit ffffffff flags c0000200 index 4
PCI: 00:00.0
PCI: 00:01.0 child on link 0 PCI: 01:05.0
PCI: 00:01.0 resource base 0 size 0 align 12 gran 12 limit 1ffffff flags 80102 index 1c
PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 81202 index 24
PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
PCI: 01:05.0
PCI: 01:05.0 resource base 0 size 8000000 align 27 gran 27 limit ffffffff flags 1200 index 10
PCI: 01:05.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 14
PCI: 01:05.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 200 index 18
PCI: 01:05.0 resource base 0 size 100000 align 20 gran 20 limit ffffffff flags 200 index 24
PCI: 00:02.0
PCI: 00:03.0
PCI: 00:04.0
PCI: 00:05.0
PCI: 00:06.0
PCI: 00:07.0
PCI: 00:08.0
PCI: 00:09.0
PCI: 00:0a.0 child on link 0 PCI: 03:00.0
PCI: 00:0a.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
PCI: 00:0a.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
PCI: 00:0a.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
PCI: 03:00.0
PCI: 03:00.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10
PCI: 03:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 1201 index 18
PCI: 03:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 1201 index 20
PCI: 03:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 2200 index 30
PCI: 00:11.0
PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
PCI: 00:11.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20
PCI: 00:11.0 resource base 0 size 400 align 12 gran 10 limit ffffffff flags 200 index 24
PCI: 00:12.0
PCI: 00:12.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
PCI: 00:12.1
PCI: 00:12.1 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
PCI: 00:12.2
PCI: 00:12.2 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 10
PCI: 00:13.0
PCI: 00:13.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
PCI: 00:13.1
PCI: 00:13.1 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
PCI: 00:13.2
PCI: 00:13.2 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 10
PCI: 00:14.0 child on link 0 I2C: 01:50
PCI: 00:14.0 resource base fec00000 size 1000 align 8 gran 8 limit ffffffff flags d0000200 index 74
PCI: 00:14.0 resource base feb00000 size 1000 align 8 gran 8 limit ffffffff flags d0000200 index 9c
PCI: 00:14.0 resource base fed00000 size 400 align 8 gran 8 limit ffffffff flags d0000200 index b4
PCI: 00:14.0 resource base b00 size 10 align 8 gran 8 limit ffff flags d0000100 index 90
PCI: 00:14.0 resource base b20 size 10 align 8 gran 8 limit ffff flags d0000100 index 58
I2C: 01:50
I2C: 01:51
I2C: 01:52
I2C: 01:53
PCI: 00:14.1
PCI: 00:14.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
PCI: 00:14.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
PCI: 00:14.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
PCI: 00:14.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
PCI: 00:14.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20
PCI: 00:14.2
PCI: 00:14.2 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
PCI: 00:14.3 child on link 0 PNP: 002e.0
PCI: 00:14.3 resource base 0 size 1 align 12 gran 0 limit ffffffff flags 200 index a0
PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
PNP: 002e.0
PNP: 002e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
PNP: 002e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
PNP: 002e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags c0000800 index 74
PNP: 002e.1
PNP: 002e.1 resource base 378 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
PNP: 002e.1 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
PNP: 002e.2
PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
PNP: 002e.3
PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
PNP: 002e.5
PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 60
PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 62
PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
PNP: 002e.5 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 72
PNP: 002e.307
PNP: 002e.8
PNP: 002e.9
PNP: 002e.109
PNP: 002e.209
PNP: 002e.309
PNP: 002e.a
PNP: 002e.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
PNP: 002e.b
PNP: 002e.b resource base 290 size 2 align 1 gran 1 limit 7ff flags c0000100 index 60
PNP: 002e.b resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
PNP: 002e.c
PNP: 002e.6
PNP: 002e.6 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 62
PCI: 00:14.4 child on link 0 PCI: 04:05.0
PCI: 00:14.4 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 81202 index 24
PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
PCI: 04:05.0
PCI: 04:05.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10
PCI: 04:05.0 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 14
PCI: 00:14.5
PCI: 00:14.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
PCI: 00:18.1
PCI: 00:18.2
PCI: 00:18.3
PCI: 00:18.3 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 200 index 94
DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
PCI: 00:18.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 00:01.0 io: base: 0 size: 0 align: 12 gran: 12 limit: 1ffffff
PCI: 01:05.0 14 * [0x0 - 0xff] io
PCI: 00:01.0 io: base: 100 size: 1000 align: 12 gran: 12 limit: ffff done
PCI: 00:0a.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
PCI: 03:00.0 10 * [0x0 - 0xff] io
PCI: 00:0a.0 io: base: 100 size: 1000 align: 12 gran: 12 limit: ffff done
PCI: 00:14.4 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 04:05.0 10 * [0x0 - 0xff] io
PCI: 00:14.4 io: base: 100 size: 1000 align: 12 gran: 12 limit: ffff done
PCI: 00:01.0 1c * [0x0 - 0xfff] io
PCI: 00:0a.0 1c * [0x1000 - 0x1fff] io
PCI: 00:14.4 1c * [0x2000 - 0x2fff] io
PCI: 00:11.0 20 * [0x3000 - 0x300f] io
PCI: 00:14.1 20 * [0x3010 - 0x301f] io
PCI: 00:11.0 10 * [0x3020 - 0x3027] io
PCI: 00:11.0 18 * [0x3028 - 0x302f] io
PCI: 00:14.1 10 * [0x3030 - 0x3037] io
PCI: 00:14.1 18 * [0x3038 - 0x303f] io
PNP: 002e.6 62 * [0x3040 - 0x3047] io
PCI: 00:11.0 14 * [0x3048 - 0x304b] io
PCI: 00:11.0 1c * [0x304c - 0x304f] io
PCI: 00:14.1 14 * [0x3050 - 0x3053] io
PCI: 00:14.1 1c * [0x3054 - 0x3057] io
PCI: 00:18.0 io: base: 3058 size: 4000 align: 12 gran: 12 limit: 7ff done
PCI: 00:18.0 00 * [0x0 - 0x3fff] io
DOMAIN: 0000 io: base: 4000 size: 4000 align: 12 gran: 0 limit: 7ff done
DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
PCI: 00:18.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff
PCI: 00:01.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff
PCI: 01:05.0 10 * [0x0 - 0x7ffffff] prefmem
PCI: 00:01.0 prefmem: base: 8000000 size: 8000000 align: 27 gran: 20 limit: ffffffff done
PCI: 00:0a.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 03:00.0 20 * [0x0 - 0x3fff] prefmem
PCI: 03:00.0 18 * [0x4000 - 0x4fff] prefmem
PCI: 00:0a.0 prefmem: base: 5000 size: 100000 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:14.4 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 00:14.4 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
PCI: 00:01.0 24 * [0x0 - 0x7ffffff] prefmem
PCI: 00:0a.0 24 * [0x8000000 - 0x80fffff] prefmem
PCI: 00:18.0 prefmem: base: 8100000 size: 8100000 align: 27 gran: 20 limit: ffffffff done
PCI: 00:18.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 00:01.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 01:05.0 24 * [0x0 - 0xfffff] mem
PCI: 01:05.0 18 * [0x100000 - 0x10ffff] mem
PCI: 00:01.0 mem: base: 110000 size: 200000 align: 20 gran: 20 limit: ffffffff done
PCI: 00:0a.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 03:00.0 30 * [0x0 - 0x1ffff] mem
PCI: 00:0a.0 mem: base: 20000 size: 100000 align: 20 gran: 20 limit: ffffffff done
PCI: 00:14.4 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 04:05.0 14 * [0x0 - 0xff] mem
PCI: 00:14.4 mem: base: 100 size: 100000 align: 20 gran: 20 limit: ffffffff done
PCI: 00:01.0 20 * [0x0 - 0x1fffff] mem
PCI: 00:0a.0 20 * [0x200000 - 0x2fffff] mem
PCI: 00:14.4 20 * [0x300000 - 0x3fffff] mem
PCI: 00:14.2 10 * [0x400000 - 0x403fff] mem
PCI: 00:12.0 10 * [0x404000 - 0x404fff] mem
PCI: 00:12.1 10 * [0x405000 - 0x405fff] mem
PCI: 00:13.0 10 * [0x406000 - 0x406fff] mem
PCI: 00:13.1 10 * [0x407000 - 0x407fff] mem
PCI: 00:14.5 10 * [0x408000 - 0x408fff] mem
PCI: 00:11.0 24 * [0x409000 - 0x4093ff] mem
PCI: 00:12.2 10 * [0x40a000 - 0x40a0ff] mem
PCI: 00:13.2 10 * [0x40b000 - 0x40b0ff] mem
PCI: 00:14.3 a0 * [0x40c000 - 0x40c000] mem
PCI: 00:18.0 mem: base: 40c001 size: 500000 align: 20 gran: 20 limit: ffffffff done
PCI: 00:18.0 02 * [0x0 - 0x80fffff] prefmem
PCI: 00:18.3 94 * [0xc000000 - 0xfffffff] mem
PCI: 00:18.0 01 * [0x10000000 - 0x104fffff] mem
DOMAIN: 0000 mem: base: 10500000 size: 10500000 align: 27 gran: 0 limit: ffffffff done
avoid_fixed_resources: DOMAIN: 0000
avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 000007ff
avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff
constrain_resources: PCI: 00:18.0 04 base 000a0000 limit 000bffff mem (fixed)
constrain_resources: PCI: 00:14.0 74 base fec00000 limit fec00fff mem (fixed)
constrain_resources: PCI: 00:14.0 9c base feb00000 limit feb00fff mem (fixed)
constrain_resources: PCI: 00:14.3 10000000 base 00000000 limit 00000fff io (fixed)
constrain_resources: PNP: 002e.2 60 base 000003f8 limit 000003ff io (fixed)
constrain_resources: PNP: 002e.3 60 base 000002f8 limit 000002ff io (fixed)
constrain_resources: PNP: 002e.5 60 base 00000060 limit 00000060 io (fixed)
constrain_resources: PNP: 002e.5 62 base 00000064 limit 00000064 io (fixed)
constrain_resources: PNP: 002e.b 60 base 00000290 limit 00000291 io (fixed)
avoid_fixed_resources:@DOMAIN: 0000 10000000 base 00000065 limit 0000028f
avoid_fixed_resources:@DOMAIN: 0000 10000100 base e8000000 limit feafffff
Setting resources...
DOMAIN: 0000 io: base:65 size:4000 align:12 gran:0 limit:28f
!! Resource didn't fit !!
aligned base 1000 size 4000 limit 28f
4fff needs to be <= 28f (limit)
PCI: 00:18.0 00 * [0x0 - 0x3fff] io
PCI: 00:18.0 00 * [0x0 - 0x3fff] io
DOMAIN: 0000 io: next_base: 65 size: 4000 align: 12 gran: 0 done
PCI: 00:18.0 io: base:0 size:4000 align:12 gran:12 limit:28f
!! Resource didn't fit !!
aligned base 0 size 1000 limit 28f
fff needs to be <= 28f (limit)
PCI: 00:01.0 1c * [0x0 - 0xfff] io
PCI: 00:01.0 1c * [0x0 - 0xfff] io
!! Resource didn't fit !!
aligned base 0 size 1000 limit 28f
fff needs to be <= 28f (limit)
PCI: 00:0a.0 1c * [0x1000 - 0x1fff] io
PCI: 00:0a.0 1c * [0x1000 - 0x1fff] io
!! Resource didn't fit !!
aligned base 0 size 1000 limit 28f
fff needs to be <= 28f (limit)
PCI: 00:14.4 1c * [0x2000 - 0x2fff] io
PCI: 00:14.4 1c * [0x2000 - 0x2fff] io
PCI: 00:11.0 20 * [0x0 - 0xf] io
PCI: 00:14.1 20 * [0x10 - 0x1f] io
PCI: 00:11.0 10 * [0x20 - 0x27] io
PCI: 00:11.0 18 * [0x28 - 0x2f] io
PCI: 00:14.1 10 * [0x30 - 0x37] io
PCI: 00:14.1 18 * [0x38 - 0x3f] io
PNP: 002e.6 62 * [0x40 - 0x47] io
PCI: 00:11.0 14 * [0x48 - 0x4b] io
PCI: 00:11.0 1c * [0x4c - 0x4f] io
PCI: 00:14.1 14 * [0x50 - 0x53] io
PCI: 00:14.1 1c * [0x54 - 0x57] io
PCI: 00:18.0 io: next_base: 58 size: 4000 align: 12 gran: 12 done
PCI: 00:01.0 io: base:0 size:1000 align:12 gran:12 limit:28f
PCI: 01:05.0 14 * [0x0 - 0xff] io
PCI: 00:01.0 io: next_base: 100 size: 1000 align: 12 gran: 12 done
PCI: 00:0a.0 io: base:1000 size:1000 align:12 gran:12 limit:28f
!! Resource didn't fit !!
aligned base 1000 size 100 limit 28f
10ff needs to be <= 28f (limit)
PCI: 03:00.0 10 * [0x0 - 0xff] io
PCI: 03:00.0 10 * [0x0 - 0xff] io
PCI: 00:0a.0 io: next_base: 1000 size: 1000 align: 12 gran: 12 done
PCI: 00:14.4 io: base:2000 size:1000 align:12 gran:12 limit:28f
!! Resource didn't fit !!
aligned base 2000 size 100 limit 28f
20ff needs to be <= 28f (limit)
PCI: 04:05.0 10 * [0x0 - 0xff] io
PCI: 04:05.0 10 * [0x0 - 0xff] io
PCI: 00:14.4 io: next_base: 2000 size: 1000 align: 12 gran: 12 done
DOMAIN: 0000 mem: base:e8000000 size:10500000 align:27 gran:0 limit:feafffff
PCI: 00:18.0 02 * [0xe8000000 - 0xf00fffff] prefmem
PCI: 00:18.3 94 * [0xf4000000 - 0xf7ffffff] mem
PCI: 00:18.0 01 * [0xf8000000 - 0xf84fffff] mem
DOMAIN: 0000 mem: next_base: f8500000 size: 10500000 align: 27 gran: 0 done
PCI: 00:18.0 prefmem: base:e8000000 size:8100000 align:27 gran:20 limit:f00fffff
PCI: 00:01.0 24 * [0xe8000000 - 0xefffffff] prefmem
PCI: 00:0a.0 24 * [0xf0000000 - 0xf00fffff] prefmem
PCI: 00:18.0 prefmem: next_base: f0100000 size: 8100000 align: 27 gran: 20 done
PCI: 00:01.0 prefmem: base:e8000000 size:8000000 align:27 gran:20 limit:efffffff
PCI: 01:05.0 10 * [0xe8000000 - 0xefffffff] prefmem
PCI: 00:01.0 prefmem: next_base: f0000000 size: 8000000 align: 27 gran: 20 done
PCI: 00:0a.0 prefmem: base:f0000000 size:100000 align:20 gran:20 limit:f00fffff
PCI: 03:00.0 20 * [0xf0000000 - 0xf0003fff] prefmem
PCI: 03:00.0 18 * [0xf0004000 - 0xf0004fff] prefmem
PCI: 00:0a.0 prefmem: next_base: f0005000 size: 100000 align: 20 gran: 20 done
PCI: 00:14.4 prefmem: base:f00fffff size:0 align:20 gran:20 limit:f00fffff
PCI: 00:14.4 prefmem: next_base: f00fffff size: 0 align: 20 gran: 20 done
PCI: 00:18.0 mem: base:f8000000 size:500000 align:20 gran:20 limit:f84fffff
PCI: 00:01.0 20 * [0xf8000000 - 0xf81fffff] mem
PCI: 00:0a.0 20 * [0xf8200000 - 0xf82fffff] mem
PCI: 00:14.4 20 * [0xf8300000 - 0xf83fffff] mem
PCI: 00:14.2 10 * [0xf8400000 - 0xf8403fff] mem
PCI: 00:12.0 10 * [0xf8404000 - 0xf8404fff] mem
PCI: 00:12.1 10 * [0xf8405000 - 0xf8405fff] mem
PCI: 00:13.0 10 * [0xf8406000 - 0xf8406fff] mem
PCI: 00:13.1 10 * [0xf8407000 - 0xf8407fff] mem
PCI: 00:14.5 10 * [0xf8408000 - 0xf8408fff] mem
PCI: 00:11.0 24 * [0xf8409000 - 0xf84093ff] mem
PCI: 00:12.2 10 * [0xf840a000 - 0xf840a0ff] mem
PCI: 00:13.2 10 * [0xf840b000 - 0xf840b0ff] mem
PCI: 00:14.3 a0 * [0xf840c000 - 0xf840c000] mem
PCI: 00:18.0 mem: next_base: f840c001 size: 500000 align: 20 gran: 20 done
PCI: 00:01.0 mem: base:f8000000 size:200000 align:20 gran:20 limit:f81fffff
PCI: 01:05.0 24 * [0xf8000000 - 0xf80fffff] mem
PCI: 01:05.0 18 * [0xf8100000 - 0xf810ffff] mem
PCI: 00:01.0 mem: next_base: f8110000 size: 200000 align: 20 gran: 20 done
PCI: 00:0a.0 mem: base:f8200000 size:100000 align:20 gran:20 limit:f82fffff
PCI: 03:00.0 30 * [0xf8200000 - 0xf821ffff] mem
PCI: 00:0a.0 mem: next_base: f8220000 size: 100000 align: 20 gran: 20 done
PCI: 00:14.4 mem: base:f8300000 size:100000 align:20 gran:20 limit:f83fffff
PCI: 04:05.0 14 * [0xf8300000 - 0xf83000ff] mem
PCI: 00:14.4 mem: next_base: f8300100 size: 100000 align: 20 gran: 20 done
Root Device assign_resources, bus 0 link: 0
node 0 : uma_memory_base/1024=0x00060000, mmio_basek=0x003a0000, basek=0x00000300, limitk=0x00080000
node 0: UMA memory starts below mmio_basek
0: mmio_basek=003a0000, basek=00000300, limitk=00080000
DOMAIN: 0000 assign_resources, bus 0 link: 0
amdk8_set_resource, enabling legacy VGA IO forwarding for PCI: 00:18.0 link 0x0
PCI: 00:18.0 1c0 <- [0x0000000000 - 0x0000003fff] size 0x00004000 gran 0x0c io <node 0 link 0>
PCI: 00:18.0 1b8 <- [0x00e8000000 - 0x00f00fffff] size 0x08100000 gran 0x14 prefmem <node 0 link 0>
PCI: 00:18.0 1b0 <- [0x00f8000000 - 0x00f84fffff] size 0x00500000 gran 0x14 mem <node 0 link 0>
PCI: 00:18.0 1a8 <- [0x00000a0000 - 0x00000bffff] size 0x00020000 gran 0x00 mem <node 0 link 0>
PCI: 00:18.0 assign_resources, bus 0 link: 0
PCI: 00:01.0 1c <- [0x0000000000 - 0x0000000fff] size 0x00001000 gran 0x0c bus 01 io
PCI: 00:01.0 24 <- [0x00e8000000 - 0x00efffffff] size 0x08000000 gran 0x14 bus 01 prefmem
PCI: 00:01.0 20 <- [0x00f8000000 - 0x00f81fffff] size 0x00200000 gran 0x14 bus 01 mem
PCI: 00:01.0 assign_resources, bus 1 link: 0
PCI: 01:05.0 10 <- [0x00e8000000 - 0x00efffffff] size 0x08000000 gran 0x1b prefmem
PCI: 01:05.0 14 <- [0x0000000000 - 0x00000000ff] size 0x00000100 gran 0x08 io
PCI: 01:05.0 18 <- [0x00f8100000 - 0x00f810ffff] size 0x00010000 gran 0x10 mem
PCI: 01:05.0 24 <- [0x00f8000000 - 0x00f80fffff] size 0x00100000 gran 0x14 mem
PCI: 00:01.0 assign_resources, bus 1 link: 0
PCI: 00:0a.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 03 io
PCI: 00:0a.0 24 <- [0x00f0000000 - 0x00f00fffff] size 0x00100000 gran 0x14 bus 03 prefmem
PCI: 00:0a.0 20 <- [0x00f8200000 - 0x00f82fffff] size 0x00100000 gran 0x14 bus 03 mem
PCI: 00:0a.0 assign_resources, bus 3 link: 0
ERROR: PCI: 03:00.0 10 io size: 0x0000000100 not assigned
PCI: 03:00.0 18 <- [0x00f0004000 - 0x00f0004fff] size 0x00001000 gran 0x0c prefmem64
PCI: 03:00.0 20 <- [0x00f0000000 - 0x00f0003fff] size 0x00004000 gran 0x0e prefmem64
PCI: 03:00.0 30 <- [0x00f8200000 - 0x00f821ffff] size 0x00020000 gran 0x11 romem
PCI: 00:0a.0 assign_resources, bus 3 link: 0
PCI: 00:11.0 10 <- [0x0000000020 - 0x0000000027] size 0x00000008 gran 0x03 io
PCI: 00:11.0 14 <- [0x0000000048 - 0x000000004b] size 0x00000004 gran 0x02 io
PCI: 00:11.0 18 <- [0x0000000028 - 0x000000002f] size 0x00000008 gran 0x03 io
PCI: 00:11.0 1c <- [0x000000004c - 0x000000004f] size 0x00000004 gran 0x02 io
PCI: 00:11.0 20 <- [0x0000000000 - 0x000000000f] size 0x00000010 gran 0x04 io
PCI: 00:11.0 24 <- [0x00f8409000 - 0x00f84093ff] size 0x00000400 gran 0x0a mem
PCI: 00:12.0 10 <- [0x00f8404000 - 0x00f8404fff] size 0x00001000 gran 0x0c mem
PCI: 00:12.1 10 <- [0x00f8405000 - 0x00f8405fff] size 0x00001000 gran 0x0c mem
PCI: 00:12.2 10 <- [0x00f840a000 - 0x00f840a0ff] size 0x00000100 gran 0x08 mem
PCI: 00:13.0 10 <- [0x00f8406000 - 0x00f8406fff] size 0x00001000 gran 0x0c mem
PCI: 00:13.1 10 <- [0x00f8407000 - 0x00f8407fff] size 0x00001000 gran 0x0c mem
PCI: 00:13.2 10 <- [0x00f840b000 - 0x00f840b0ff] size 0x00000100 gran 0x08 mem
PCI: 00:14.0 assign_resources, bus 1 link: 0
PCI: 00:14.0 assign_resources, bus 1 link: 0
PCI: 00:14.1 10 <- [0x0000000030 - 0x0000000037] size 0x00000008 gran 0x03 io
PCI: 00:14.1 14 <- [0x0000000050 - 0x0000000053] size 0x00000004 gran 0x02 io
PCI: 00:14.1 18 <- [0x0000000038 - 0x000000003f] size 0x00000008 gran 0x03 io
PCI: 00:14.1 1c <- [0x0000000054 - 0x0000000057] size 0x00000004 gran 0x02 io
PCI: 00:14.1 20 <- [0x0000000010 - 0x000000001f] size 0x00000010 gran 0x04 io
PCI: 00:14.2 10 <- [0x00f8400000 - 0x00f8403fff] size 0x00004000 gran 0x0e mem64
PCI: 00:14.3 a0 <- [0x00f840c000 - 0x00f840c000] size 0x00000001 gran 0x00 mem
PCI: 00:14.3 assign_resources, bus 0 link: 0
PNP: 002e.2 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io
PNP: 002e.2 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq
PNP: 002e.3 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io
PNP: 002e.3 70 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 irq
PNP: 002e.5 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io
PNP: 002e.5 62 <- [0x0000000064 - 0x0000000064] size 0x00000001 gran 0x00 io
PNP: 002e.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq
ERROR: PNP: 002e.5 72 irq size: 0x0000000001 not assigned
PNP: 002e.b 60 <- [0x0000000290 - 0x0000000291] size 0x00000002 gran 0x01 io
ERROR: PNP: 002e.b 70 irq size: 0x0000000001 not assigned
PNP: 002e.6 62 <- [0x0000000040 - 0x0000000047] size 0x00000008 gran 0x03 io
PCI: 00:14.3 assign_resources, bus 0 link: 0
PCI: 00:14.4 1c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x0c bus 04 io
PCI: 00:14.4 24 <- [0x00f00fffff - 0x00f00ffffe] size 0x00000000 gran 0x14 bus 04 prefmem
PCI: 00:14.4 20 <- [0x00f8300000 - 0x00f83fffff] size 0x00100000 gran 0x14 bus 04 mem
PCI: 00:14.4 assign_resources, bus 4 link: 0
ERROR: PCI: 04:05.0 10 io size: 0x0000000100 not assigned
PCI: 04:05.0 14 <- [0x00f8300000 - 0x00f83000ff] size 0x00000100 gran 0x08 mem
PCI: 00:14.4 assign_resources, bus 4 link: 0
PCI: 00:14.5 10 <- [0x00f8408000 - 0x00f8408fff] size 0x00001000 gran 0x0c mem
PCI: 00:18.0 assign_resources, bus 0 link: 0
PCI: 00:18.3 94 <- [0x00f4000000 - 0x00f7ffffff] size 0x04000000 gran 0x1a mem <gart>
DOMAIN: 0000 assign_resources, bus 0 link: 0
Root Device assign_resources, bus 0 link: 0
Done setting resources.
Show resources in subtree (Root Device)...After assigning values.
Root Device child on link 0 CPU_CLUSTER: 0
CPU_CLUSTER: 0 child on link 0 APIC: 00
APIC: 00
DOMAIN: 0000 child on link 0 PCI: 00:18.0
DOMAIN: 0000 resource base 65 size 4000 align 12 gran 0 limit 28f flags 40040100 index 10000000
DOMAIN: 0000 resource base e8000000 size 10500000 align 27 gran 0 limit feafffff flags 40040200 index 10000100
DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 10
DOMAIN: 0000 resource base c0000 size 1ff40000 align 0 gran 0 limit 0 flags e0004200 index 20
DOMAIN: 0000 resource base 18000000 size 8000000 align 0 gran 0 limit 0 flags f0000200 index 7
PCI: 00:18.0 child on link 0 PCI: 00:00.0
PCI: 00:18.0 resource base 0 size 4000 align 12 gran 12 limit 28f flags 60080100 index 1c0
PCI: 00:18.0 resource base e8000000 size 8100000 align 27 gran 20 limit f00fffff flags 60081200 index 1b8
PCI: 00:18.0 resource base f8000000 size 500000 align 20 gran 20 limit f84fffff flags 60080200 index 1b0
PCI: 00:18.0 resource base a0000 size 20000 align 0 gran 0 limit ffffffff flags e0000200 index 1a8
PCI: 00:00.0
PCI: 00:01.0 child on link 0 PCI: 01:05.0
PCI: 00:01.0 resource base 0 size 1000 align 12 gran 12 limit 28f flags 60080102 index 1c
PCI: 00:01.0 resource base e8000000 size 8000000 align 27 gran 20 limit efffffff flags 60081202 index 24
PCI: 00:01.0 resource base f8000000 size 200000 align 20 gran 20 limit f81fffff flags 60080202 index 20
PCI: 01:05.0
PCI: 01:05.0 resource base e8000000 size 8000000 align 27 gran 27 limit efffffff flags 60001200 index 10
PCI: 01:05.0 resource base 0 size 100 align 8 gran 8 limit ff flags 60000100 index 14
PCI: 01:05.0 resource base f8100000 size 10000 align 16 gran 16 limit f810ffff flags 60000200 index 18
PCI: 01:05.0 resource base f8000000 size 100000 align 20 gran 20 limit f80fffff flags 60000200 index 24
PCI: 00:02.0
PCI: 00:03.0
PCI: 00:04.0
PCI: 00:05.0
PCI: 00:06.0
PCI: 00:07.0
PCI: 00:08.0
PCI: 00:09.0
PCI: 00:0a.0 child on link 0 PCI: 03:00.0
PCI: 00:0a.0 resource base 1000 size 1000 align 12 gran 12 limit 28f flags 60080102 index 1c
PCI: 00:0a.0 resource base f0000000 size 100000 align 20 gran 20 limit f00fffff flags 60081202 index 24
PCI: 00:0a.0 resource base f8200000 size 100000 align 20 gran 20 limit f82fffff flags 60080202 index 20
PCI: 03:00.0
PCI: 03:00.0 resource base 0 size 100 align 8 gran 8 limit 28f flags 100 index 10
PCI: 03:00.0 resource base f0004000 size 1000 align 12 gran 12 limit f0004fff flags 60001201 index 18
PCI: 03:00.0 resource base f0000000 size 4000 align 14 gran 14 limit f0003fff flags 60001201 index 20
PCI: 03:00.0 resource base f8200000 size 20000 align 17 gran 17 limit f821ffff flags 60002200 index 30
PCI: 00:11.0
PCI: 00:11.0 resource base 20 size 8 align 3 gran 3 limit 27 flags 60000100 index 10
PCI: 00:11.0 resource base 48 size 4 align 2 gran 2 limit 4b flags 60000100 index 14
PCI: 00:11.0 resource base 28 size 8 align 3 gran 3 limit 2f flags 60000100 index 18
PCI: 00:11.0 resource base 4c size 4 align 2 gran 2 limit 4f flags 60000100 index 1c
PCI: 00:11.0 resource base 0 size 10 align 4 gran 4 limit f flags 60000100 index 20
PCI: 00:11.0 resource base f8409000 size 400 align 12 gran 10 limit f84093ff flags 60000200 index 24
PCI: 00:12.0
PCI: 00:12.0 resource base f8404000 size 1000 align 12 gran 12 limit f8404fff flags 60000200 index 10
PCI: 00:12.1
PCI: 00:12.1 resource base f8405000 size 1000 align 12 gran 12 limit f8405fff flags 60000200 index 10
PCI: 00:12.2
PCI: 00:12.2 resource base f840a000 size 100 align 12 gran 8 limit f840a0ff flags 60000200 index 10
PCI: 00:13.0
PCI: 00:13.0 resource base f8406000 size 1000 align 12 gran 12 limit f8406fff flags 60000200 index 10
PCI: 00:13.1
PCI: 00:13.1 resource base f8407000 size 1000 align 12 gran 12 limit f8407fff flags 60000200 index 10
PCI: 00:13.2
PCI: 00:13.2 resource base f840b000 size 100 align 12 gran 8 limit f840b0ff flags 60000200 index 10
PCI: 00:14.0 child on link 0 I2C: 01:50
PCI: 00:14.0 resource base fec00000 size 1000 align 8 gran 8 limit ffffffff flags d0000200 index 74
PCI: 00:14.0 resource base feb00000 size 1000 align 8 gran 8 limit ffffffff flags d0000200 index 9c
PCI: 00:14.0 resource base fed00000 size 400 align 8 gran 8 limit ffffffff flags d0000200 index b4
PCI: 00:14.0 resource base b00 size 10 align 8 gran 8 limit ffff flags d0000100 index 90
PCI: 00:14.0 resource base b20 size 10 align 8 gran 8 limit ffff flags d0000100 index 58
I2C: 01:50
I2C: 01:51
I2C: 01:52
I2C: 01:53
PCI: 00:14.1
PCI: 00:14.1 resource base 30 size 8 align 3 gran 3 limit 37 flags 60000100 index 10
PCI: 00:14.1 resource base 50 size 4 align 2 gran 2 limit 53 flags 60000100 index 14
PCI: 00:14.1 resource base 38 size 8 align 3 gran 3 limit 3f flags 60000100 index 18
PCI: 00:14.1 resource base 54 size 4 align 2 gran 2 limit 57 flags 60000100 index 1c
PCI: 00:14.1 resource base 10 size 10 align 4 gran 4 limit 1f flags 60000100 index 20
PCI: 00:14.2
PCI: 00:14.2 resource base f8400000 size 4000 align 14 gran 14 limit f8403fff flags 60000201 index 10
PCI: 00:14.3 child on link 0 PNP: 002e.0
PCI: 00:14.3 resource base f840c000 size 1 align 12 gran 0 limit f840c000 flags 60000200 index a0
PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
PNP: 002e.0
PNP: 002e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
PNP: 002e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
PNP: 002e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags c0000800 index 74
PNP: 002e.1
PNP: 002e.1 resource base 378 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
PNP: 002e.1 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
PNP: 002e.2
PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60
PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
PNP: 002e.3
PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60
PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
PNP: 002e.5
PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 60
PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 62
PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
PNP: 002e.5 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 72
PNP: 002e.307
PNP: 002e.8
PNP: 002e.9
PNP: 002e.109
PNP: 002e.209
PNP: 002e.309
PNP: 002e.a
PNP: 002e.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
PNP: 002e.b
PNP: 002e.b resource base 290 size 2 align 1 gran 1 limit 7ff flags e0000100 index 60
PNP: 002e.b resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
PNP: 002e.c
PNP: 002e.6
PNP: 002e.6 resource base 40 size 8 align 3 gran 3 limit 47 flags 60000100 index 62
PCI: 00:14.4 child on link 0 PCI: 04:05.0
PCI: 00:14.4 resource base 2000 size 1000 align 12 gran 12 limit 28f flags 60080102 index 1c
PCI: 00:14.4 resource base f00fffff size 0 align 20 gran 20 limit f00fffff flags 60081202 index 24
PCI: 00:14.4 resource base f8300000 size 100000 align 20 gran 20 limit f83fffff flags 60080202 index 20
PCI: 04:05.0
PCI: 04:05.0 resource base 0 size 100 align 8 gran 8 limit 28f flags 100 index 10
PCI: 04:05.0 resource base f8300000 size 100 align 12 gran 8 limit f83000ff flags 60000200 index 14
PCI: 00:14.5
PCI: 00:14.5 resource base f8408000 size 1000 align 12 gran 12 limit f8408fff flags 60000200 index 10
PCI: 00:18.1
PCI: 00:18.2
PCI: 00:18.3
PCI: 00:18.3 resource base f4000000 size 4000000 align 26 gran 26 limit f7ffffff flags 60000200 index 94
Done allocating resources.
Enabling resources...
PCI: 00:18.0 cmd <- 00
PCI: 00:18.1 subsystem <- 1022/3060
PCI: 00:18.1 cmd <- 00
PCI: 00:18.2 subsystem <- 1022/3060
PCI: 00:18.2 cmd <- 00
PCI: 00:18.3 cmd <- 00
PCI: 00:00.0 subsystem <- 1022/3060
PCI: 00:00.0 cmd <- 06
PCI: 00:01.0 bridge ctrl <- 000b
PCI: 00:01.0 cmd <- 074.8
coreboot-4.8.1-dirty Wed May 16 19:00:17 UTC 2018 romstage starting...
bsp_apicid=0x0
01 nodes initialized.
NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead.
core0 started:
NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead.
NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead.
SBLink=00
NC node|link=00
rs780_early_setup()
k8_optimization()
rs780_por_init
sb700_early_setup()
sb700_devices_por_init()
sb700_devices_por_init(): SMBus Device, BDF:0-20-0
SMBus controller enabled, sb revision is A14
sb700_devices_por_init(): IDE Device, BDF:0-20-1
sb700_devices_por_init(): LPC Device, BDF:0-20-3
sb700_devices_por_init(): P2P Bridge, BDF:0-20-4
sb700_devices_por_init(): SATA Device, BDF:0-17-0
sb700_pmio_por_init()
begin msr fid, vid: hi=0x12040606, lo=0x40a0a0a
NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead.
Current fid_cur: 0xa, fid_max: 0xa
Requested fid_new: 0xa
end msr fid, vid: hi=0x12040604, lo=0x40a0a0a
rs780_htinit cpu_ht_freq=6.
rs780_htinit: HT1 mode
needs_reset=0x1
ht reset -
soft_reset() called!
coreboot-4.8.1-dirty Wed May 16 19:00:17 UTC 2018 romstage starting...
bsp_apicid=0x0
01 nodes initialized.
NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead.
core0 started:
NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead.
NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead.
SBLink=00
NC node|link=00
rs780_early_setup()
k8_optimization()
rs780_por_init
sb700_early_setup()
sb700_devices_por_init()
sb700_devices_por_init(): SMBus Device, BDF:0-20-0
SMBus controller enabled, sb revision is A14
sb700_devices_por_init(): IDE Device, BDF:0-20-1
sb700_devices_por_init(): LPC Device, BDF:0-20-3
sb700_devices_por_init(): P2P Bridge, BDF:0-20-4
sb700_devices_por_init(): SATA Device, BDF:0-17-0
sb700_pmio_por_init()
begin msr fid, vid: hi=0x12040604, lo=0x40a0a0a
NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead.
end msr fid, vid: hi=0x12040604, lo=0x40a0a0a
rs780_htinit cpu_ht_freq=6.
rs780_htinit: HT1 mode
needs_reset=0x0
sysinfo->nodes: 1 sysinfo->ctrl: 000c8128 spd_addr: fff0b3bc
Ram1.00
Ram2.00
NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead.
NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead.
Setting DualDIMMen
NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead.
RAM end at 0x00080000 kB
Ram3
Initializing memory: done
Ram4
BSP overran lower stack boundary. Undefined behaviour may result!
Romstage handoff structure not added!